LT3758 datasheet(19/28 Pages) AD

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LT8392

Rev. 0

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APPLICATIONS INFORMATION

Switch C operates in boost region as the control switch.

Its power dissipation at maximum current is given by:

PC(BOOST) =

VOUT − VIN

(

)• VOUT

VIN 2

•IOUT(MAX)

2 • ρT

•RDS(ON) + k • VOUT3 •

IOUT(MAX)

VIN

• CRSS • f

where CRSS is usually specified by the MOSFET manufac-

turers. The constant k, which accounts for the loss caused

by reverse recovery current, is inversely proportional to

the gate drive current and has an empirical value of 1.7.

For switch D, the maximum power dissipation happens in

boost region, when its duty cycle is higher than 50%. Its

maximum power dissipation at maximum output current

is given by:

PD(BOOST) =

VOUT

VIN

•IOUT(MAX)

2 • ρT •RDS(ON)

For the same output voltage and current, switch A has the

highest power dissipation and switch B has the lowest

power dissipation unless a short occurs at the output.

From a known power dissipated in the power MOSFET, its

junction temperature can be obtained using the following

formula:

TJ = TA + P • RTH(JA)

The junction-to-ambient thermal resistance RTH(JA)

includes the junction-to-case thermal resistance RTH(JC)

and the case-to-ambient thermal resistance RTH(CA). This

value of TJ can then be compared to the original, assumed

value used in the iterative calculation process.

Optional Schottky Diode (DB, DD) Selection

The optional Schottky diodes DB (in parallel with switch

B) and DD (in parallel with switch D) conduct during the

dead time between the conduction of the power MOSFET

switches. They are intended to prevent the body diode

of synchronous switches B and D from turning on and

storing charge during the dead time. In particular, DB

significantly reduces reverse recovery current between

switch B turn-off and switch A turn-on, and DD signifi-

cantly reduces reverse recovery current between switch

D turn-off and switch C turn-on. They improve converter

efficiency and reduce switch voltage stress. In order for

the diode to be effective, the inductance between it and

the synchronous switch must be as small as possible,

mandating that these components be placed adjacently.

CIN and COUT Selection

Input and output capacitance is necessary to suppress

voltage ripple caused by discontinuous current moving

in and out the regulator. A parallel combination of capac-

itors is typically used to achieve high capacitance and low

equivalent series resistance (ESR). Dry tantalum, special

polymer, aluminum electrolytic and ceramic capacitors are

all available in surface mount packages. Capacitors with

low ESR and high ripple current ratings, such as OS-CON

and POSCAP are also available.

Ceramic capacitors should be placed near the regulator

input and output to suppress high frequency switching

spikes. Ceramic capacitors, of at least 1µF, should also

be placed from VIN to GND and VOUT to GND as close to

the LT8392 pins as possible. Due to their excellent low

ESR characteristics, ceramic capacitors can significantly

reduce input ripple voltage and help reduce power loss

in the higher ESR bulk capacitors. X5R or X7R dielec-

trics are preferred, as these materials retain their capac-

itance over wide voltage and temperature ranges. Many

ceramic capacitors, particularly 0805 or 0603 case sizes,

have greatly reduced capacitance at the desired operating

voltage.

Input Capacitance CIN: Discontinuous input current is

highest in the buck region due to the switch A toggling

on and off. Make sure that the CIN capacitor network has

low enough ESR and is sized to handle the maximum RMS

current. In buck region, the input RMS current is given by:

IRMS ≈IOUT(MAX) •

VOUT

VIN

•

VIN

VOUT

− 1

The formula has a maximum at VIN = 2VOUT, where IRMS

= IOUT(MAX)/2. This simple worst-case condition is com-

monly used for design because even significant deviations

do not offer much relief.

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