P8/14

Rev. M, Aug 2012

ML1001

Note :

1.

In cascade format of ML1001 (ie. ML1001-2U and –3U), one pin is the input of current ML1001 and

the other is for the connection with the corresponding input pin of next ML1001.

2. All Enable pins are active low.

3. Condition : FIN = 32 KHz Clock.

Pin Description

Symbol

Pad

Description

LOAD

1,28

Load data from the shift register to data register; note 1

DIN

2

Display data input pin

DCLK

3,26

Input pin for the clock of the display data; note 1

BEN

4,25

Enable pin of the blink function; note 1, note 2

OEN

5

Enable pin of the internal oscillator; note 2

6

Supply voltage

SEN1

7

Enable pin of the segment from S1 to S16; note 1

CEN1A

8

Enable pin of the COM1A; note 2

SEN2

9

Enable pin of the segment from S17 to S40; note 1

CEN1B

10

Enable pin of the COM1B; note 2

GND

11

Logic ground

OOUT

12

Output pin of the internal oscillator

FIN

13

Input pin of the external/internal clock

LCLK

14,24

Input pin to the LCD display clock; note 1

2 kHz

15

Output 1/16 frequency of the input to the FIN; note 3

1 kHz

16

Output 1/32 frequency of the input to the FIN; note 3

512 Hz

17

Output 1/64 frequency of the input to the FIN; note 3

256 Hz

18

Output 1/128 frequency of the input to the FIN; note 3

128 Hz

19

Output 1/256 frequency of the input to the FIN; note 3

4 Hz

20

Output 1/8192 frequency of the input to the FIN; note 3

2 Hz

21

Output 1/16384 frequency of the input to the FIN; note 3

1 Hz

22

Output 1/32768 frequency of the input to the FIN; note 3

BCLK

23

Input pin for the blink clock

DOUT

27

Output pin for 40-bit Shift register, it shall connect to DIN of next ML1001

GND

29

Logic ground

30

Supply voltage

COM1B

31

Common driving signal to LCD panel

S40 to S1

32 to 71

LCD segment outputs

COM1A

72

Common driving signal to LCD panel

73

Supply voltage

GND

74

Logic ground