PTN3361CBSMP datasheet(22/30 Pages) NXP

22 / 30 page

PTN3361C

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.1 — 28 July 2015

22 of 30

NXP Semiconductors

PTN3361C

HDMI/DVI level shifter supporting 1.65 Gbit/s operation

11.5 DDC characteristics

[1]

VCC1 is the pull-up voltage for DDC source.

[2]

IOL between 100 A and 6 mA guaranteed by design (3 mA typical application)

[3]

VCC2 is the pull-up voltage for DDC sink.

Table 15.

DDC characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Input and output SCL_SOURCE and SDA_SOURCE, VCC1 = 3.0 V to 3.6 V[1]

VIH

HIGH-level input voltage

0.7VCC1

-3.6

VIL

LOW-level input voltage

0.5

+0.3VCC1

VILc

contention LOW-level input voltage

guaranteed by design

0.5

0.4

ILI

input leakage current

VI =3.6 V

A

IIL

LOW-level input current

VI =0.2 V

A

VOL

LOW-level output voltage

IOL =6mA

[2] 0.47

0.52

0.6

VOLVILc

difference between LOW-level output

and LOW-level input voltage

contention

guaranteed by design

Cio

input/output capacitance

VI =3 V or 0 V; VDD =3.3 V

VI = 3 V or 0 V; VDD =0V

Input and output SDA_SINK and SCL_SINK, VCC2 =4.5 V to 5.5V[3]

VIH

HIGH-level input voltage

0.7VCC2

-5.5

VIL

LOW-level input voltage

0.5

+1.2

ILI

input leakage current

VI =5.5 V

A

IIL

LOW-level input current

VI =0.2 V

A

VOL

LOW-level output voltage

IOL =6mA

0.1

0.2

Cio

input/output capacitance

VI =3 V or 0 V; VDD =3.3 V

VI = 3 V or 0 V; VDD =0V

Itrt(pu)

transient boosted pull-up current

VCC2 =4.5 V;

slew rate = 1.25 V/

s

-6

-mA

PTN3361CBSMP Datasheet(PDF) 22 Page - NXP Semiconductors

PTN3361CBSMP Datasheet(HTML) 22 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

Datasheet Download

Link URL