PCF8536AT datasheet(12/48 Pages) NXP

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PCE85176AUG

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Product data sheet

Rev. 1 — 12 January 2015

12 of 48

NXP Semiconductors

PCE85176AUG

4 × 40 LCD segment driver for Chip-On-Glass

7.3.2 Writing to RAM in 1:3 multiplex drive mode

In 1:3 multiplex drive mode, the RAM is written as shown in Table 18 (see Figure 4 as

well).

If the bit at position BP2/S2 would be written by a second byte transmitted, then the

mapping of the segment bits would change as illustrated in Table 19.

In the case described in Table 19 the RAM has to be written entirely and BP2/S2, BP2/S5,

BP2/S8 etc. have to be connected to elements on the display. This can be achieved by a

combination of writing and rewriting the RAM like follows:

• In the first write to the RAM, bits a7 to a0 are written.

• The data-pointer (see Section 7.3.1 on page 11) has to be set to the address of bit a1

• In the second write, bits b7 to b0 are written, overwriting bits a1 and a0 with bits b7

and b6.

• The data-pointer has to be set to the address of bit b1

• In the third write, bits c7 to c0 are written, overwriting bits b1 and b0 with bits c7 and

c6.

Depending on the method of writing to the RAM (standard or entire filling by rewriting),

some elements remain unused or can be used. But it has to be considered in the module

layout process as well as in the driver software design.

7.3.3 Writing over the RAM address boundary

In all multiplex drive modes, depending on the setting of the data pointer, it is possible to

fill the RAM over the RAM address boundary. In this case, the additional bits will be

discarded.

Table 18.

Standard RAM filling in 1:3 multiplex drive mode

Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are not connected to any elements on the display.

Display RAM

bits (rows)/

backplane

outputs (BPn)

Display RAM addresses (columns)/segment outputs (Sn)

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Table 19.

Entire RAM filling by rewriting in 1:3 multiplex drive mode

Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are connected to elements on the display.

Display RAM

bits (rows)/

backplane

outputs (BPn)

Display RAM addresses (columns)/segment outputs (Sn)

a1/b7 b4

b1/c7 c4

c1/d7 d4

d1/e7 e4

a0/b6 b3

b0/c6 c3

c0/d6 d3

d0/e6 e3

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