SPC584B64E3 datasheet(26/142 Pages) STMICROELECTRONICS

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Electrical characteristics

SPC584Bx

26/142

DS11701 Rev 4

4.8

I/O pad specification

The following table describes the different pad type configurations.

Note:

Each I/O pin on the device supports specific drive configurations. See the signal description

table in the device reference manual for the available drive configurations for each I/O pin.

PMC_DIG_VSIO register has to be configured to select the voltage level (3.3 V or 5.0 V) for

each IO segment.

Logic level is configurable in running mode while it is CMOS not-configurable in STANDBY

for LP (low power) pads, so if a LP pad is used to wakeup from STANDBY, it should be

configured as CMOS also in running mode in order to prevent device wrong behavior in

STANDBY.

4.8.1

I/O input DC characteristics

The following table provides input DC electrical characteristics, as described in Figure 3.

Table 9. I/O pad specification descriptions

Pad type

Description

Weak configuration

Provides a good compromise between transition time and low electromagnetic emission.

Medium configuration

Provides transition fast enough for the serial communication channels with controlled

current to reduce electromagnetic emission.

Strong configuration

Provides fast transition speed; used for fast interface.

Very strong

configuration

Provides maximum speed and controlled symmetric behavior for rise and fall transition.

Used for fast interface including Ethernet interface requiring fine control of rising/falling

edge jitter.

Differential

configuration

A few pads provide differential capability providing very fast interface together with good

EMC performances.

Input only pads

These low input leakage pads are associated with the ADC channels.

Standby pads

These pads (LP pads) are active during STANDBY. They are configured in CMOS level

logic and this configuration cannot be changed. Moreover, when the device enters the

STANDBY mode, the pad-keeper feature is activated for LP pads. It means that:

– if the pad voltage level is above the pad keeper high threshold, a weak pull-up resistor

is automatically enabled

– if the pad voltage level is below the pad keeper low threshold, a weak pull-down resistor

is automatically enabled.

For the pad-keeper high/low thresholds, consider(VDD_HV_IO_MAIN / 2) +/-20 %.

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