MPC8535EEC datasheet(48/127 Pages) NXP

48 / 127 page

MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7

Electrical Characteristics

Freescale Semiconductor

Figure 22. TBI Transmit AC Timing Diagram

2.9.2.4.2

TBI Receive AC Timing Specifications

This table provides the TBI receive AC timing specifications.

Table 33. TBI Receive AC Timing Specifications

At recommended operating conditions with L/TVDD of 3.3 V ± 5%.

Parameter/Condition2

Symbol 1

Min

Typ

Max

Unit

Clock period for TBI Receive Clock 0, 1

tTRX

—

16.0

—

Skew for TBI Receive Clock 0, 1

tSKTRX

7.5

—

8.5

Duty cycle for TBI Receive Clock 0, 1

tTRXH/tTRX

—

RCG[9:0] setup time to rising edge of TBI Receive Clock 0, 1

tTRDVKH

2.5

—

RCG[9:0] hold time to rising edge of TBI Receive Clock 0, 1

tTRDXKH

1.5

—

Clock rise time (20%-80%) for TBI Receive Clock 0, 1

tTRXR

0.7

—

2.4

Clock fall time (80%-20%) for TBI Receive Clock 0, 1

tTRXF

0.7

—

2.4

Note:

1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)

for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tTRDVKH symbolizes TBI receive

timing (TR) with respect to the time data input signals (D) reach the valid state (V) relative to the tTRX clock reference (K) going

to the high (H) state or setup time. Also, tTRDXKH symbolizes TBI receive timing (TR) with respect to the time data input signals

(D) went invalid (X) relative to the tTRX clock reference (K) going to the high (H) state. Note that, in general, the clock reference

symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of

tTRX represents the TBI (T) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter:

R (rise) or F (fall). For symbols representing skews, the subscript is skew (SK) followed by the clock that is being skewed (TRX).

2. The signals “TBI Receive Clock 0” and “TBI Receive Clock 1” refer to TSECn_RX_CLK and TSECn_TX_CLK pins respectively.

These two clock signals are also referred as PMA_RX_CLK[0:1].

GTX_CLK

TCG[9:0]

tTTXR

tTTX

tTTXH

tTTXR

tTTXF

tTTKHDV

tTTKHDX

tTTXF

MPC8535EEC Datasheet(PDF) 48 Page - NXP Semiconductors

MPC8535EEC Datasheet(HTML) 48 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL