MPC8535EEC datasheet(98/127 Pages) NXP

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MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7

Electrical Characteristics

Freescale Semiconductor

Figure 67. Single-Ended Measurement Points for Rise and Fall Time Matching

The other detailed AC requirements of the SerDes Reference Clocks is defined by each interface protocol based on application

usage. See the following sections for detailed information:

•

Section 2.9.3.2, “AC Requirements for SGMII SD2_REF_CLK and SD2_REF_CLK”

•

Section 2.21.2, “AC Requirements for PCI Express SerDes Clocks”

2.20.2.4.1

Spread Spectrum Clock

SD1_REF_CLK/SD1_REF_CLK were designed to work with a spread spectrum clock (+0 to -0.5% spreading at 30–33 kHz

rate is allowed), assuming both ends have same reference clock. For better results, a source without significant unintended

modulation should be used.

SD2_REF_CLK/SD2_REF_CLK are not intended to be used with, and should not be clocked by, a spread spectrum clock

source.

2.20.3

SerDes Transmitter and Receiver Reference Circuits

This figure shows the reference circuits for SerDes data lane’s transmitter and receiver.

Figure 68. SerDes Transmitter and Receiver Reference Circuits

The DC and AC specification of SerDes data lanes are defined in each interface protocol section below (PCI Express, SATA or

SGMII) in this document based on the application usage:

•

Section 2.9.3, “SGMII Interface Electrical Characteristics”

•

Section 2.21, “PCI Express”

•

Section 2.16, “Serial ATA (SATA)”

Please note that external AC Coupling capacitor is required for the above three serial transmission protocols with the capacitor

value defined in specification of each protocol section.

SDn_REF_CLK

VCROSS MEDIAN

VCROSS MEDIAN + 100 mV

VCROSS MEDIAN – 100 mV

TFALL

TRISE

Receiver

Transmitter

SD1_TXn or

SD2_TXn

SD1_TXn or

SD2_TXn

SD1_RXn or

SD2_RXn

SD1_RXn or

SD2_RXn

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