MPC8535EEC datasheet(102/127 Pages) NXP

102 / 127 page

MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7

Electrical Characteristics

Freescale Semiconductor

102

2.21.4.2

Transmitter Compliance Eye Diagrams

The TX eye diagram in Figure 69 is specified using the passive compliance/test measurement load (see Figure 71) in place of

any real PCI Express interconnect + RX component.

There are two eye diagrams that must be met for the transmitter. Both eye diagrams must be aligned in time using the jitter

median to locate the center of the eye diagram. The different eye diagrams will differ in voltage depending whether it is a

transition bit or a de-emphasized bit. The exact reduced voltage level of the de-emphasized bit will always be relative to the

transition bit.

The eye diagram must be valid for any 250 consecutive UIs.

A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is created using all edges

of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX UI.

NOTE

It is recommended that the recovered TX UI is calculated using all edges in the 3500

consecutive UI interval with a fit algorithm using a minimization merit function (that is,

least squares and median deviation fits).

Figure 69. Minimum Transmitter Timing and Voltage Output Compliance Specifications

VTX-DIFF = 0 mV

(D+ D– Crossing Point)

[De-Emphasized Bit]

0.07 UI = UI – 0.3 UI (JTX-TOTAL-MAX)

566 mV (3 dB ) >=

VTX-DIFFp-p-MIN >= 505 mV (4 dB )

[Transition Bit]

VTX-DIFFp-p-MIN = 800 mV

VRX-DIFF = 0 mV

(D+ D– Crossing Point)

[Transition Bit]

VTX-DIFFp-p-MIN = 800 mV

MPC8535EEC Datasheet(PDF) 102 Page - NXP Semiconductors