MPC8535EEC datasheet(116/127 Pages) NXP

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MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7

Hardware Design Considerations

Freescale Semiconductor

116

To measure Z0 for the single-ended drivers, an external resistor is connected from the chip pad to OVDD or GND. Then, the

value of each resistor is varied until the pad voltage is OVDD/2 (see Figure 77). The output impedance is the average of two

components, the resistances of the pull-up and pull-down devices. When data is held high, SW1 is closed (SW2 is open) and

RP is trimmed until the voltage at the pad equals OVDD/2. RP then becomes the resistance of the pull-up devices. RP and RN

are designed to be close to each other in value. Then, Z0 = (RP + RN)/2.

Figure 77. Driver Impedance Measurement

This table summarizes the signal impedance targets. The driver impedances are targeted at minimum VDD, nominal OVDD,

105

°C.

3.9

Configuration Pin Muxing

The chip provides the user with power-on configuration options which can be set through the use of external pull-up or

pull-down resistors of 4.7 k

Ω on certain output pins (see customer visible configuration pins). These pins are generally used as

output only pins in normal operation.

While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins while HRESET is

asserted, is latched when HRESET deasserts, at which time the input receiver is disabled and the I/O circuit takes on its normal

function. Most of these sampled configuration pins are equipped with an on-chip gated resistor of approximately 20 k

Ω. This

value should permit the 4.7-k

Ω resistor to pull the configuration pin to a valid logic low level. The pull-up resistor is enabled

only during HRESET (and for platform /system clocks after HRESET deassertion to ensure capture of the reset value). When

the input receiver is disabled the pull-up is also, thus allowing functional operation of the pin as an output with minimal signal

quality or delay disruption. The default value for all configuration bits treated this way has been encoded such that a high voltage

level puts the chip into the default state and external resistors are needed only when non-default settings are required by the user.

Table 81. Impedance Characteristics

Impedance

Local Bus, Ethernet, DUART,

Control, Configuration, Power

Management

PCI

DDR DRAM

Symbol Unit

45 Target

45 Target (cfg_pci_impd=1)

25 Target (cfg_pci_impd=0)

18 Target (full strength mode)

36 Target (full strength mode)

45 Target

45 Target (cfg_pci_impd=1)

25 Target (cfg_pci_impd=0)

18 Target (full strength mode)

36 Target (full strength mode)

Note: Nominal supply voltages. See Table 1.

OVDD

OGND

Pad

Data

SW1

SW2

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