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AD630ADZ Datasheet(PDF) 15 Page - Analog Devices

Part # AD630ADZ
Description  Balanced Modulator/Demodulator
PDF  20 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD630ADZ Datasheet(HTML) 15 Page - Analog Devices

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Data Sheet
AD630
Rev. G | Page 15 of 20
OFFSET VOLTAGE NULLING
The offset voltages of both input stages and the comparator
have been pretrimmed so that external trimming is only required
in the most demanding applications. The offset adjustment of
the two input channels is accomplished by means of a differential
and common-mode scheme. This facilitates fine adjustment of
system errors in switched gain applications. With the system
input tied to 0 V, and a switching or carrier waveform applied
to the comparator, a low level square wave appears at the output.
The differential offset adjustment potentiometers can be used
to null the amplitude of this square wave (Pin 3 and Pin 4).
The common-mode offset adjustment can be used to zero the
residual dc output voltage (Pin 5 and Pin 6). Implement these
functions using 10 kΩ trim potentiometers with wipers
connected directly to Pin 8 as shown in Figure 28 and
Figure 29.
CHANNEL STATUS OUTPUT
The channel status output, Pin 7, is an open collector output
referenced to −VS that can be used to indicate which of the two
input channels is active. The output is active (pulled low) when
Channel A is selected. This output can also be used to supply
positive feedback around the comparator. This produces
hysteresis which serves to increase noise immunity. Figure 26
shows an example of how hysteresis may be implemented. Note
that the feedback signal is applied to the inverting (−) terminal
of the comparator to achieve positive feedback. This is because
the open collector channel status output inverts the output
sense of the internal comparator.
Figure 26. Comparator Hysteresis
The channel status output may be interfaced with TTL inputs
as shown in Figure 27. This circuit provides appropriate level
shifting from the open-collector AD630 channel status output
to TTL inputs.
Figure 27. Channel Status—TTL Interface
1MΩ
100kΩ
100kΩ
–15V
+5V
100Ω
7
8
9
10
–15V
+5V
TTL INPUT
AD630
+15V
IN914s
6.8kΩ
22kΩ
100kΩ
2N2222
7
8



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