LPC55S2X datasheet(41/132 Pages) NXP

41 / 132 page

LPC55S2x/LPC552x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2.1 — 6 August 2021

41 of 132

NXP Semiconductors

LPC55S2x/LPC552x

32-bit ARM Cortex-M33 microcontroller

7. Functional description

7.1 Architectural overview

The Arm Cortex M33 includes two AHB-Lite buses, one system bus and one code and

bus. The Code AHB (C-AHB) interface is used for any instruction fetch and data access to

the Code region of the ARMv8-M memory map ([0x00000000 - 0x1FFFFFFF]). The

System AHB (S-AHB) interface is used for instruction fetch and data access to all other

regions of the ARMv8-M memory map ([0x20000000 - 0xFFFFFFFF]).

The LPC55S2x/LPC552x uses a multi-layer AHB matrix to connect the ARM Cortex-M33

buses and other bus masters to peripherals in a flexible manner that optimizes

performance by allowing peripherals that are on different slave ports of the matrix to be

accessed simultaneously by different bus masters. Figure 3 “LPC55S2x/LPC552x Block

Diagram” shows details of the available matrix connections.

7.2 Arm Cortex-M33 processor

The ARM Cortex-M33 is based on the ARMv8-M architecture that offers systems

enhancements, such as single-cycle digital signal processing, low power consumption,

enhanced debug features, and a high level of support block integration. The ARM

Cortex-M33 CPU employs a 7-stage instruction pipe and includes an internal prefetch unit

that supports speculative branching. A hardware floating-point processor is integrated into

the core. On the LPC55S2x/LPC552x, the Cortex-M33 is augmented with two hardware

co-processors providing accelerated support for additional DSP algorithms and

cryptography.

7.3 Arm Cortex-M33 integrated Floating Point Unit (FPU)

The FPU fully supports single-precision add, subtract, multiply, divide, multiply and

accumulate, and square root operations. It also provides conversions between fixed-point

and floating-point data formats, and floating-point constant instructions.

The FPU provides floating-point computation functionality that is compliant with the

ANSI/IEEE Std 754-2008, IEEE Standard for Binary Floating-Point Arithmetic, referred to

as the IEEE 754 standard.

7.4 Memory Protection Unit (MPU)

The Cortex-M33 includes a Memory Protection Unit (MPU) which can be used to improve

the reliability of an embedded system by protecting critical data within the user

application.

The MPU allows separating processing tasks by disallowing access to each other's data,

disabling access to memory regions, allowing memory regions to be defined as read-only

and detecting unexpected memory accesses that could potentially break the system.

The MPU separates the memory into distinct regions and implements protection by

preventing disallowed accesses. The MPU supports up to eight regions each of which can

be divided into eight subregions. Accesses to memory locations that are not defined in the

MPU regions, or not permitted by the region setting, will cause the Memory Management

Fault exception to take place.

LPC55S2X Datasheet(PDF) 41 Page - NXP Semiconductors

LPC55S2X Datasheet(HTML) 41 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL