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71M6545/71M6545H Data Sheet

Table 20: Timers/Counters Mode Description

Mode

Function

Mode 0

13-bit Counter/Timer mode with 5 lower bits in the TL0 or TL1 (SFR

0x8A or SFR 0x8B) register and the remaining 8 bits in the TH0 or TH1

(SFR 0x8C or SFR 0x8D) register (for Timer 0 and Timer 1, respectively).

The 3 high order bits of TL0 and TL1 are held at zero.

Mode 1

16-bit Counter/Timer mode.

Mode 2

8-bit auto-reload Counter/Timer. The reload value is kept in TH0 or

TH1, while TL0 or TL1 is incremented every machine cycle. When

TL(x) overflows, a value from TH(x) is copied to TL(x) (where x is 0 for

counter/timer 0 or 1 for counter/timer 1.

Mode 3

If Timer 1 M1 and M0 bits are set to 1, Timer 1 stops.

If Timer 0 M1 and M0 bits are set to 1, Timer 0 acts as two independent

8-bit Timer/Counters.

In Mode 3, TL0 is affected by TR0 and gate control bits, and sets the TF0 flag on overflow, while TH0

is affected by the TR1 bit, and the TF1 flag is set on overflow. Table 21 specifies the combinations of

operation modes allowed for Timer 0 and Timer 1.

Table 21: Allowed Timer/Counter Mode Combinations

Timer 1

Mode 0

Mode 1

Mode 2

Timer 0 - mode 0

Yes

Timer 0 - mode 1

Yes

Timer 0 - mode 2

Not allowed

Yes

Table 22: TMOD Register Bit Description (SFR 0x89)

Bit

Symbol

Function

Timer/Counter 0:

TMOD[7]

Gate

If TMOD[7] is set, external input signal control is enabled for Counter 0. The

TR0 bit in the TCON register (SFR 0x88) must also be set in order for Counter

0 to increment. With these settings, Counter 0 increments on every falling

edge of the logic signal applied to one or more of the DIO2-11 pins, as

specified by the contents of the DIO_R2 through DIO_R11 registers. See

Table 47.

TMOD[6]

C/T

Selects timer or counter operation. When set to 1, a counter operation is

performed. When cleared to 0, the corresponding register functions as a timer.

TMOD[5:4]

M1:M0

Selects the mode for Timer/Counter 0 as shown in Table 20.

Timer/Counter 1

TMOD[3]

Gate

If TMOD[3] is set, external input signal control is enabled for Counter 1.

The TR1 bit in the TCON register (SFR 0x88) must also be set in order for

Counter 1 to increment. With these settings, Counter 1 increments on every

falling edge of the logic signal applied to one or more of the DIO2-11 pins,

as specified by the contents of the DIO_R2 through DIO_R11 registers. See

Table 47.

TMOD[2]

C/T

Selects timer or counter operation. When set to 1, a counter operation is

performed. When cleared to 0, the corresponding register functions as a

timer.

TMOD[1:0]

M1:M0

Selects the mode for Timer/Counter 1, as shown in Table 20.

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