1- to 3-Cell, High-Current, Low-Noise,

Step-Up DC-DC Converters with Linear Regulator

12

______________________________________________________________________________________

current limit for the MAX1705, and 950mA (max) for the

MAX1706. During PWM operation, the circuit operates

with a continuous inductor current.

Synchronized PWM Operation

The MAX1705/MAX1706 can also be synchronized to a

200kHz to 400kHz frequency by applying an external

clock to CLK/SEL. This allows the user to set the har-

monics, to avoid IF bands in wireless applications. The

synchronous rectifier is also active during synchronized

PWM operation.

Low-Power PFM Operation

Pulling CLK/SEL low places the MAX1705/MAX1706 in

low-power standby mode. During standby mode, PFM

operation regulates the output voltage by transferring a

fixed amount of energy during each cycle, and then

modulating the switching frequency to control the

power delivered to the output. The devices switch only

as needed to service the load, resulting in the highest

possible efficiency at light loads. Output current capa-

bility in PFM mode is 140mA (from 2.4V input to 3.3V

output). The output is regulated at 1.3% above the

PWM threshold.

During PFM operation, the error comparator detects

output voltage falling out of regulation and sets a

flip-flop, turning on the n-channel MOSFET switch

(Figure 4). When the inductor current ramps to the PFM

mode current limit (435mA) and stores a fixed amount

of energy, the current-sense comparator resets a flip-

flop. The flip-flop turns off the n-channel switch and

turns on the p-channel synchronous rectifier. A second

flip-flop, previously reset by the switch’s “on” signal,

inhibits the error comparator from initiating another

cycle until the energy stored in the inductor is dumped

into the output filter capacitor and the synchronous rec-

tifier current ramps down to 70mA. This forces opera-

tion with a discontinuous inductor current.

Synchronous Rectifier

The MAX1705/MAX1706 feature an internal 270m

Ω,

p-channel synchronous rectifier to enhance efficiency.

Synchronous rectification provides a 5% efficiency

improvement over similar nonsynchronous step-up

regulators. In PWM mode, the synchronous rectifier is

turned on during the second half of each cycle. In PFM

mode, an internal comparator turns on the synchronous

rectifier when the voltage at LX exceeds the step-up

converter output, and then turns it off when the inductor

current drops below 70mA.

Linear Regulator

The internal low-dropout linear regulator steps down the

output from the step-up converter and reduces switching

ripple. It is intended to power noise-sensitive analog cir-

cuitry, such as low-noise amplifiers and IF stages in cel-

lular phones and other instruments, and can deliver up to

200mA. However, in practice, the maximum output cur-

rent is further limited by the current available from the

boost converter and by the voltage differential between

OUT and LDO. Use a 22µF capacitor with a 1

Ω or less

equivalent series resistance (ESR) at the output for sta-

bility (see the Linear Regulator Region of Stable C6 ESR

vs. Load Current graph in the Typical Operating

Characteristics). When the MAX1705/1706 are activated

by logic control (ONA, ONB), the linear regulator (LDO)

remains off until the step-up converter (POUT) goes into

POUT

LX

PGND

P

N

S

Q

ICS

R

IFB*

IREF*

CURRENT-

LIMIT LEVEL

OSC

*SEE FIGURE 1

N

LX

PGND

IFB*

IREF*

CURRENT-

LIMIT LEVEL

S

Q

R

Q

Q

R

D

LOGIC HIGH

POUT

P

*SEE FIGURE 1

Figure 3. Simplified PWM Controller Block Diagram

Figure 4. Controller Block Diagram in PFM Mode