HS7512 datasheet(6/6 Pages) SIPEX

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SIGNAL PROCESSING EXCELLENCE

118

TIMING

INPUT

DATA

t 1

t 2

LBE

MBE

HBE

LDAC

OUTPUT

t 2

t 4

TIME AXIS NOT TO SCALE. ALL STROBES ARE LEVEL TRIGGERED.

1: Data Setup Time, Time data must be stable before strobe (byte enable/

LDAC) goes to “0”, t

1 (min) = 250ns.

2: Strobe Width. t2 (min) = 250ns. (CE, LBE, MBE, HBE, LDAC).

3: Hold Time. Time data must be stable after strobe goes to “0”, t3 = 0ns.

4: Delay from LDAC to Output, t4 = 200ns.

NOTE: Minimum common active time for CE and any byte enable is 250ns.

ORDERING INFORMATION

Model .................................................................. Monotonicity ................................. Temperature Range ........................................ Package

Double–Buffered 12–Bit Multiplying DAC

SP7512BN ............................................................... 12–Bit ......................................... –40

°C to +85°C ......................................28-pin, 0.3" SOIC

SP7512KN ............................................................... 12–Bit .............................................. 0

°C to +70°C ......................................28-pin, 0.3" SOIC

HS3120C–2N ........................................................... 12–Bit .............................................. 0

°C to +70°C ............................ 28-pin, 0.6" Plastic DIP

HS3120C–2Q ........................................................... 12–Bit .............................................. 0

°C to +70°C .................. 28-pin, 0.6" Side–Brazed DIP

HS3120B–2Q ........................................................... 12–Bit ....................................... –55

°C to +125°C .................. 28-pin, 0.6" Side–Brazed DIP

HS3120B–2/883 ...................................................... 12–Bit ....................................... –55

°C to +125°C .................. 28-pin, 0.6" Side–Brazed DIP

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