SIC437 datasheet(8/27 Pages) VISHAY

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SiC437, SiC438

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Vishay Siliconix

S20-0679-Rev. D, 27-Aug-2020

Document Number: 75921

For technical questions, contact: powerictechsupport@vishay.com

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

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Output Undervoltage Protection (UVP)

UVP is implemented by monitoring the FB pin. If the voltage

level at FB drops below 0.12 V for more than 25 μs, a UVP

event is recognized and both high side and low side

MOSFETs are turned off. After a duration equivalent to

20 soft start periods, the IC attempts to re-start. If the fault

condition still exists, the above cycle will be repeated.

UVP is active after the completion of soft start sequence.



Output Overvoltage Protection (OVP)

OVP is implemented by monitoring the FB pin. If the voltage

level at FB rising above 0.72 V, a OVP event is recognized

and both high side and low side MOSFETs are turned off.

Normal operation is resumed once FB voltage drop below

0.68 V.

OOVP is active after VDD passes UVLO rising threshold.

Over-Temperature Protection (OTP)

OTP

implemented

monitoring

the

junction

temperature. If the junction temperature rises above 150 °C,

a OTP event is recognized and both high side and low

MOSFETs are turned off. After the junction temperature falls

below 125 °C (25 °C hysteresis), the device restarts by

initiating a soft start sequence.



Sequencing of Input / Output Supplies

SiC437, SiC438 have no sequencing requirements on its

supplies or enables (VIN, VDD, VDRV, EN).

Enable

The SiC437, SiC438 have an enable pin to turn the part on

and off.

Driving the pin high enables the device, while driving the pin

low disables the device.

The EN pin is internally pulled to AGND by a 5 M resistor to

prevent unwanted turn on due to a floating GPIO.



Pre-Bias Start-Up

In case of pre-bias startup, output is monitored through FB

pin. If the sensed voltage on FB is higher than the internal

reference ramp value, control logic prevents high side and

low side MOSFETs from switching to avoid negative output

voltage spike and excessive current sinking through low

side MOSFET.

Fig. 8 - Pre-Bias Start-Up

Power Good

SiC437, SiC438 power good is an open-drain output. Pull

PGOOD pin high through a > 10 k resistor to use this signal.

Power good window is shown in the below diagram. If

voltage on FB pin is out of this window, PGOOD signal is

de-asserted by pulling down to AGND. To prevent false

triggering during transient events, PGOOD has a 25 μs

blanking time.

Fig. 9 - PGOOD Window Diagram



Vref (0.6 V)

VFB

VFB_Rising_Vth_OV

(typ. = 0.72 V)

VFB_Falling_Vth_OV

(typ. = 0.68 V)

VFB_Falling_Vth_UV

(typ. = 0.54 V)

VFB_Rising_Vth_UV

(typ. = 0.58 V)

Pull-high

Pull-low

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