NTS0102GD datasheet(14/38 Pages) NXP

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NXP Semiconductors

NTS0102

Dual supply translating transceiver; open-drain; auto direction sensing

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1.8 V

SYSTEM

CONTROLLER

3.3 V

SYSTEM

1.8 V

3.3 V

0.1 µF

1 µF

VCC(A)

DATA

NTS0102

VCC(B)

Figure 9. Typical operating circuit

13.2 Architecture

The architecture of the NTS0102 is shown in Figure 10. The device does not require an

extra input signal to control the direction of data flow from A to B or B to A.

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VCC(A)

VCC(B)

10 kΩ

ONE

SHOT

ONE

SHOT

GATE BIAS

Figure 10. Architecture of NTS0102 I/O cell (one channel)

The NTS0102 is a "switch" type voltage translator, it employs two key circuits to enable

voltage translation:

1. A pass-gate transistor (N-channel) that ties the ports together.

2. An output edge-rate accelerator that detects and accelerates rising edges on the I/O

pins.

The gate bias voltage of the pass gate transistor (T3) is set at approximately one

threshold voltage above the VCC level of the low-voltage side. During a LOW-to-HIGH

transition, the output one-shot accelerates the output transition by switching on the

PMOS transistors (T1, T2) bypassing the 10 kΩ pull-up resistors and increasing current

drive capability. The one-shot is activated once the input transition reaches approximately

VCCI/2; it is de-activated approximately 50 ns after the output reaches VCCO/2. During the

acceleration time, the driver output resistance is between approximately 50 Ω and 70 Ω.

To avoid signal contention and minimize dynamic ICC, the user should wait for the one-

shot circuit to turn-off before applying a signal in the opposite direction. Pull-up resistors

are included in the device for DC current sourcing capability.

NTS0102

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 20 April 2022

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