LPC1102 datasheet(32/43 Pages) NXP

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LPC1102_1104

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Product data sheet

Rev. 7 — 26 September 2013

32 of 43

NXP Semiconductors

LPC1102/1104

32-bit ARM Cortex-M0 microcontroller

10.5 I/O pins

[1]

Applies to standard port pins and RESET pin.

10.6 SPI interfaces

[1]

Tcy(clk) = (SSPCLKDIV  (1 + SCR)  CPSDVSR) / fmain. The clock cycle time derived from the SPI bit rate Tcy(clk) is a function of the

main clock frequency fmain, the SPI peripheral clock divider (SSPCLKDIV), the SPI SCR parameter (specified in the SSP0CR0 register),

and the SPI CPSDVSR parameter (specified in the SPI clock prescale register).

[2]

Tamb = 40 C to 85 C.

[3]

Tcy(clk) = 12  Tcy(PCLK).

[4]

Tamb = 25 C; for normal voltage supply range: VDD = 3.3 V.

Table 13.

Dynamic characteristic: I/O pins[1]

Tamb = 40 C to +85 C; 3.0 V  VDD  3.6 V.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

rise time

configured as

output

3.0

5.0

fall time

configured as

output

2.5

5.0

Table 14.

Dynamic characteristics of SPI pins in SPI mode

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

SPI master (in SPI mode)

Tcy(clk)

clock cycle time

when only receiving

[1]

when only transmitting [1]

tDS

data set-up time

in SPI mode

2.4 V

 V

DD  3.6 V

[2]

2.0 V

 V

DD < 2.4 V

[2]

1.8 V

 V

DD < 2.0 V

[2]

tDH

data hold time

in SPI mode

[2]

tv(Q)

data output valid time in SPI mode

[2]

th(Q)

data output hold time in SPI mode

[2]

SPI slave (in SPI mode)

Tcy(PCLK)

PCLK cycle time

tDS

data set-up time

in SPI mode

[3][4]

tDH

data hold time

in SPI mode

[3][4]

 T

cy(PCLK) + 4

tv(Q)

data output valid time in SPI mode

[3][4]

 T

cy(PCLK) + 11

th(Q)

data output hold time in SPI mode

[3][4]

 T

cy(PCLK) + 5

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