10 Layout

10.1 Layout Guidelines

Two layers are sufficient to accomplish a low EMI PCB design.

• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their

inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits

of the data link.

• For best performance, it is recommended to minimize the length of D+/D- board traces from the MCU to

ISOUSB111, and from ISOUSB111 to the connector. Vias and stubs on D+/D- lines must be avoided.

• Placing a solid ground plane just below the high-speed signal layer establishes controlled impedance for

transmission line interconnects and provides an excellent low-inductance path for the return current flow.

D+ and D- traces must be designed for 90-Ω differential impedance and as close to 45-Ω single ended

impedance as possible.

• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of

• Decoupling capacitors must be placed on the top layer, and the routing between the capacitors and the

corresponding to supply and ground pins must be completed in the top layer itself. There should not be any

vias in the routing path between the decoupling capacitors and the corresponding supply and ground pins.

• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links

usually have margin to tolerate discontinuities such as vias.

10.1.1 Layout Example

The layout example in this section shows the recommended placement for de-coupling capacitors and ESD

protection diodes. A continuous ground plane is recommended below the D+/D- signal traces. Small footprint

capacitors (0402/0201) are recommended so that these may be placed very close to the supply pins and

corresponding ground pins and connected using the top layer. There should not be any vias in the routing path

between the decoupling capacitors and the corresponding supply and ground pins. The ESD protection diodes

should be placed close to the connector with a strong connection to the ground plane. The example shown is for

an isolated host or hub, but similar considerations apply for isolated peripherals also. The 120-μF capacitor on

VBUS only applies to host or hub and should not be used for peripherals. A ferrite bead, with dc resistance less

than 100 mΩ, may be optionally placed on the VBUS route, after the 100-nF (and 120-μF) capacitors to prevent

transients such as ESD from affecting the rest of the circuits.

For best performance, it is recommended to minimize the length of D+/D- board traces from the MCU to

ISOUSB111, and from ISOUSB111 to the connector. Vias and stubs on D+/D- lines must be avoided.

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ISOUSB111

SLLSFC6A – NOVEMBER 2021 – REVISED APRIL 2022

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