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TUSB1142 Datasheet(PDF) 4 Page - Texas Instruments |
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TUSB1142 Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 55 page ![]() Table 4-1. Pin Functions (continued) PIN TYPE(1) DESCRIPTION NAME NO. RSVD1 9 I Reserved. Leave pin unconnected RSVD2 10 I Reserved. Leave pin unconnected NC 11 No internal connection. RSVD3 12 O Reserved. Leave pin unconnected RSVD4 13 O Reserved. Leave pin unconnected. VIO_SEL 14 4-level I (PU/PD) Selects the input thresholds for I2C (SDA and SCL). "0": I2C 3.3 V "R": I2C 1.8 V "F": I2C 3.3 V. "1": I2C 1.8 V. SSTXn 15 I Differential negative input for USB port. Should be connected to USB 3.2 Host transmit port through an external 220 nF AC-coupling capacitor. SSTXp 16 I Differential positive input for USB port. Should be connected to USB 3.2 Host transmit port through an external 220 nF AC-coupling capacitor. MODE 17 4-level I (PU/PD) This pin selects whether device is in I2C mode or pin-strap mode. Refer to Table 7-5 for details. SSRXn 18 O Differential negative output for USB port. Should be connected to USB 3.2 Host receiver port through an external 220 nF AC-coupling capacitor. SSRXp 19 O Differential positive output for USB port. Should be connected to USB 3.2 Host receiver port through an external 220 nF AC-coupling capacitor. VCC 20 P 3.3 V supply FLIP/SCL 21 I In I2C mode, this pin functions as I2C clock. In pin-strap In pin-strap mode, this pin controls the orientation of the MUX (Refer to Table 7-4). AEQENZ/SDA 22 I/O In I2C mode, this pin functions as I2C data. In pin-strap mode, this pin controls whether or not AEQ is enabled. 0: AEQ enabled 1: AEQ disabled AEQCFG 23 4-level I (PU/PD) In pin-strap mode, this pin controls the FULLAEQ_UPPER_EQ limit. In I2C mode, this function is controlled by the FULLAEQ_UPPER_EQ register. "0": FULLAEQ_UPPER_EQ = Ah "R": FULLAEQ_UPPER_EQ = Fh "F": FULLAEQ_UPPER_EQ = 8h "1": FULLAEQ_UPPER_EQ = Ch NC 24 No internal connection NC 25 No internal connection EN 26 I (PU) When low, the differential receiver's termination will be disabled and differential drivers will be disabled. On rising edge of EN, device will sample four-level inputs and function based on the sampled state of the pins. This pin has a internal 500k pull-up to VCC. Please note this pin will also reset internal configuration registers. TEST1 27 I TI Test1. Under normal operations, this pin shall be connected directly or pull-down to GND. VCC 28 P 3.3 V supply CEQ1 29 4-level I (PU/PD) In pin-strap mode, this pin along with CEQ0 selects the receiver EQ for CRX1 and/or CRX2 (Refer to Table 7-2). CRX1p 30 I Differential positive input for USB port 1. Should be connected to RX1p pin of USB connector. Connection can be DC-coupled to USB connector. Optionally, connection can be through an external 330 nF AC-coupling capacitor. CRX1n 31 I Differential negative input for USB port 1. Should be connected to RX1n pin of USB connector. Connection can be DC-coupled to USB connector. Optionally, connection can be through an external 330 nF AC-coupling capacitor. NC 32 No internal connection. TUSB1142 SLLSFL2 – APRIL 2022 www.ti.com 4 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TUSB1142 |
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