Pin

Name

LLP Pin

Number

I/O, Type

Description

POWER

V

DD

2, 6, 12,

37, 43,

46, 48

I, Power

V

GND

3, 47

(Note 2)

I, Power

Ground reference for LVDS and CMOS circuitry.

For the LLP package, the DAP is used as the primary GND connection to the device. The

DAP is the exposed metal contact at the bottom of the LLP-48 package. It should be

connected to the ground plane with at least 4 vias for optimal AC and thermal performance.

Note 1: For interfacing LVDS outputs to CML or LVPECL compatible inputs, refer to the applications section of this datasheet (planned).

Note 2: Note that the DAP on the backside of the LLP package is the primary GND connection for the device when using the LLP package.

Note 3: The LVDS outputs do not support a multidrop (BLVDS) environment. The LVDS output characteristics of the DS15MB200 device have been optimized for

point-to-point backplane and cable applications.

Connection Diagrams

20157302

LLP Top View

DAP = GND

20157303

Directional Signal Paths Top View

(Refer to pin names for signal polarity)

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