LM6211 datasheet(12/19 Pages) NSC

12 / 19 page

Application Notes (Continued)

In the Loop Compensation

Figure 2 illustrates a compensation technique, known as ‘in

the loop’ compensation, that employs an RC feedback circuit

within the feedback loop to stabilize a non-inverting amplifier

configuration. A small series resistance, R

S, is used to iso-

late the amplifier output from the load capacitance, C

L, and a

small capacitance, C

F, is inserted across the feedback re-

sistor to bypass C

L at higher frequencies.

The values for R

S and CF are decided by ensuring that the

zero attributed to C

F lies at the same frequency as the pole

attributed to C

L. This ensures that the effect of the second

pole on the transfer function is compensated for by the

presence of the zero, and that the ROC is maintained at

20 dB/decade. For the circuit shown in Figure 2 the values of

S and CF are given by Equation (1). Table 1 shows different

values of R

S and CF that need to be used for maintaining

stability with different values of C

L, as well as the phase

margins to be expected. R

F and RIN are assumed to be 10

Ω,R

L is taken as 2 k

Ω, while R

OUT is taken to be 60

Ω.

(1)

TABLE 1.

L (pF)

S (

Ω)C

F (pF)

Phase Margin (˚)

250

4.5

39.8

300

5.4

49.5

500

53.1

Although this methodology provides circuit stability for any

load capacitance, it does so at the price of bandwidth. The

closed loop bandwidth of the circuit is now limited by R

S and

Compensation by External Resistor

In some applications it is essential to drive a capacitive load

without sacrificing bandwidth. In such a case, in the loop

compensation is not viable. A simpler scheme for compen-

sation is shown in Figure 3. A resistor, R

ISO, is placed in

series between the load capacitance and the output. This

introduces a zero in the circuit transfer function, which coun-

teracts the effect of the pole formed by the load capacitance,

and ensures stability.

The value of R

ISO to be used should be decided depending

on the size of C

L and the level of performance desired.

Values ranging from 5

Ω to 50Ω are usually sufficient to

ensure stability. A larger value of R

ISO will result in a system

with lesser ringing and overshoot, but will also limit the

output swing and the short circuit current of the circuit.

Stability and Input Capacitance

In certain applications, for example I-V conversion, transim-

pedance photodiode amplification and buffering the output of

current-output DAC, capacitive loading at the input of the op

amp can endanger stability. The capacitance of the source

driving the op amp, the op amp input capacitance and the

parasitic/wiring capacitance contribute to the loading of the

input. This capacitance, C

IN, interacts with the feedback

network to introduce a peaking in the closed loop gain of the

circuit, and hence causes instability.

This peaking can be eliminated by adding a feedback ca-

pacitance, C

F, as shown in Figure 4. This introduces a zero

in the feedback network, and hence a pole in the closed loop

response, and thus maintains stability. An optimal value of

F is given by Equation (2). A simpler approach is to select

F =(R1/R2)CIN for a 90˚ phase margin. This approach,

however, limits the bandwidth excessively.

20120338

FIGURE 2. In the Loop Compensation

20120356

FIGURE 3. Compensation By Isolation Resistor

20120349

FIGURE 4. Compensating for Input Capacitance

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