GS9062 datasheet(39/46 Pages) GENNUM

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GS9062 Data Sheet

22209 - 5

May 2005

39 of 46

3.10.3 Configuration and Status Registers

Table 3-11 summarizes the GS9062's internal status and configuration registers.

All of these registers are available to the host via the GSPI and are all individually

addressable.

Where status registers contain less than the full 16 bits of information however, two

or more registers may be combined at a single logical address.

3.11 JTAG

When the JTAG/HOST input pin of the GS9062 is set HIGH, the host interface port

will be configured for JTAG test operation. In this mode, pins 27 through 30

become TMS, TDO, TDI, and TCK. In addition, the RESET_TRST pin will operate

as the test reset pin.

Boundary scan testing using the JTAG interface will be enabled in this mode.

There are two methods in which JTAG can be used on the GS9062:

1. As a stand-alone JTAG interface to be used at in-circuit ATE (Automatic Test

Equipment) during PCB assembly; or

2. Under control of the host for applications such as system power on self tests.

When the JTAG tests are applied by ATE, care must be taken to disable any other

devices driving the digital I/O pins. If the tests are to be applied only at ATE, this

can be accomplished with tri-state buffers used in conjunction with the

JTAG/HOST input signal. This is shown in Figure 3-10.

Table 3-11: GS9062 Internal Registers

Address

See Section

00h

IOPROC_DISABLE

Section 3.6.3

02h

EDH_FLAG

Section 3.6.3.3

04h

VIDEO_STANDARD

Section 3.6.2

0Ah - 0Bh

VIDEO_FORMAT

Section 3.6.3.1

0Eh - 11h

RASTER_STRUCTURE

Section 3.6.2

12h - 19h

EDH_CALC_RANGES

Section 3.6.3.3

1Bh - 1Ch

LINE_352M

Section 3.6.3.1

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