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ADG3231 Datasheet(PDF) 3 Page - Analog Devices

Part # ADG3231
Description  1.65 V to 3.6 V, Single-Channel Level Translator in SOT-23 Package
PDF  12 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADG3231 Datasheet(HTML) 3 Page - Analog Devices

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Data Sheet
ADG3231
Rev. C | Page 3 of 12
SPECIFICATIONS
VCC1 = VCC2 = 1.65 V to 3.6 V, GND = 0 V. All specifications TMIN to TMAX, unless otherwise noted. Temperature range for the B version is
−40°C to +85°C.
Table 1.
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
LOGIC INPUTS/OUTPUTS
Input High Voltage2
VIH
VCC1 = 3.0 V to 3.6 V
1.35
V
VCC1 = 2.3 V to 2.7 V
1.35
V
VCC1 = 1.65 V to 1.95 V
0.65 VCC1
V
Input Low Voltage2
VIL
VCC1 = 3.0 V to 3.6 V
0.8
V
VCC1 = 2.3 V to 2.7 V
0.7
V
VCC1 = 1.65 V to 1.95 V
0.35 VCC1
V
Output High Voltage
VOH
IOH = –100 μA, VCC2 = 3.0 V to 3.6 V
2.4
V
IOH = –100 μA, VCC2 = 2.3 V to 2.7 V
2.0
V
IOH = –100 μA, VCC2 = 1.65 V to 1.95 V
VCC2 − 0.45
V
IOH = −4 mA, VCC2 = 2.3 V to 2.7 V
2.0
V
IOH = −4 mA, VCC2 = 1.65 V to 1.95 V
VCC2 − 0.45
V
IOH = −8 mA, VCC2 = 3.0 V to 3.6 V
2.4
V
Output Low Voltage
VOL
IOL = 100 μA, VCC2 = 3.0 V to 3.6 V
0.4
V
IOL = 100 μA, VCC2 = 2.3 V to 2.7 V
0.4
V
IOL = 100 μA, VCC2 = 1.65 V to 1.95 V
0.45
V
IOL = 4 mA, VCC2 = 2.3 V to 2.7 V
0.4
V
IOL = 4 mA, VCC2 = 1.65 V to 1.95 V
0.45
V
IOL = 8 mA, VCC2 = 3.0 V to 3.6 V
0.4
V
SWITCHING CHARACTERISTICS2
Propagation Delay, tPD A to Y
tPHL, tPLH
3.3 V ± 0.3 V, CL = 30 pF, see Figure 2
4
6.5
ns
Propagation Delay, tPD A to Y
tPHL, tPLH
2.5 V ± 0.2 V, CL = 30 pF, see Figure 2
4.5
6.5
ns
Propagation Delay, tPD A to Y
tPHL, tPLH
1.8 V ± 0.15 V, CL = 30 pF, see Figure 2
6.5
10.25
ns
Input Leakage Current
II
0 ≤ VIN ≤ 3.6 V
±1
μA
Output Leakage Current
IO
0 ≤ VIN ≤ 3.6 V
±1
μA
POWER REQUIREMENTS
Power Supply Voltages
VCC1
1.65
3.6
V
VCC2
1.65
3.6
V
Quiescent Power Supply Current
ICC1
Digital inputs = 0 V or VCC1
2
μA
ICC2
Digital inputs = 0 V or VCC2
2
μA
1 All typical values are at VCC1 = VCC2, TA = 25°C, unless otherwise noted.
2 Guaranteed by design, not subject to production test.
INPUT
0V
VCC2
0V
VCC1
50%
50%
tPLH
tPHL
OUTPUT
Figure 2. Timing Diagram



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