DAC63002 datasheet(52/85 Pages) TI

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7.5.2.3 I2C Read Sequence

To read any register the following command sequence must be used:

1. Send a start or repeated start command with a target address and the R/W bit set to 0 for writing. The device

acknowledges this event.

2. Send a command byte for the register to be read. The device acknowledges this event again.

3. Send a repeated start with the target address and the R/W bit set to 1 for reading. The device acknowledges

this event.

4. The device writes the MSDB byte of the addressed register. The controller must acknowledge this byte.

5. Finally, the device writes out the LSDB of the register.

The broadcast address cannot be used for reading.

Table 7-17. Read Sequence

MSB

…

R/W

(0)

ACK

MSB

…

LSB

ACK

Sr MSB …

R/W

(1)

ACK

MSB

…

LSB

ACK

MSB

…

LSB

ACK

Address byte

Section 7.5.2.2.1

Command byte

Section 7.5.2.2.2

Address byte

Section 7.5.2.2.1

MSDB

LSDB

From controller

Target

From controller

Target

From controller

Target

From target

Controller

From Target

Controller

7.5.3 General-Purpose Input/Output (GPIO) Modes

Together with I2C and SPI, the DACx300x also support a GPIO that can be configured in the NVM for multiple

functions. This pin allows for updating the DAC output channels and reading status bits without using the

programming interface, thus enabling processor-less operation. In the GPIO-CONFIG register, write 1 to the

GPI-EN bit to set the GPIO pin as an input, or write 1 to the GPO-EN bit to set the pin as output. There

are global and channel-specific functions mapped to the GPIO pin. For channel-specific functions, select the

channels using the GPI-CH-SEL field in the GPIO-CONFIG register. Table 7-18 lists the functional options

available for the GPIO as input and Table 7-19 lists the options for the GPIO as output. Some of the GP input

operations are edge-triggered after the device boots up. After the power supply ramps up, the device registers

the GPI level and executes the associated command. This feature allows the user to configure the initial output

state at power-on. By default, the GPIO pin is not mapped to any operation. When the GPIO pin is mapped to

a specific input function, the corresponding software bit functionality is disabled to avoid a race condition. When

used as a RESET input, the GPIO pin must transmit an active-low pulse for triggering a device reset. All other

constraints of the functions are applied to the GPIO-based trigger.

Note

Pull the GPIO pin high or low when not used. When the GPIO pin is used as RESET, the configuration

must be programmed into the NVM. Otherwise, the setting is cleared after the device resets.

DAC53001, DAC53002, DAC63001, DAC63002

SLASF48 – MAY 2022

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Product Folder Links: DAC53001 DAC53002 DAC63001 DAC63002

DAC63002 Datasheet(PDF) 52 Page - Texas Instruments

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