DRV8452SPWPR datasheet(52/117 Pages) TI

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STEP

ISTSL

TRQ_DAC

tSTSL_DLY tSTSL_FALL

Figure 7-33. Standstill Power Saving Mode

Note

• TSTSL_FALL in production samples will be 1/16 th of their value in the pre-production samples.

For example, TSTSL_FALL = 0001b will mean fall time for each current step will be 1 ms.

• If ISTSL has to be changed while the device is in standstill power saving mode, first cycle the

EN_STSL bit from 1b to 0b and back to 1b.

7.4.14 Charge Pump

A charge pump is integrated to supply the high-side N-channel MOSFET gate-drive voltage. The charge pump

requires a capacitor between the VM and VCP pins to act as the storage capacitor. Additionally a ceramic

capacitor is required between the CPH and CPL pins to act as the flying capacitor.

VCP

1 μF

CPH

Charge

Pump

Control

CPL

0.1 μF

Figure 7-34. Charge Pump Block Diagram

7.4.15 Linear Voltage Regulator

A linear voltage regulator is integrated in the device. When the VCC pin is connected to DVDD, the DVDD

regulator provides power to the low-side gate driver and all the internal circuits. For proper operation, bypass the

DVDD pin to GND using a 1 μF ceramic capacitor. The DVDD output is nominally 5-V.

DRV8452

SLOSE84 – AUGUST 2022

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DRV8452SPWPR Datasheet(PDF) 52 Page - Texas Instruments