DRV8452SPWPR datasheet(21/117 Pages) TI

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• SPI_STEP:

– When this bit is '0', the stepping depends on the STEP pin inputs.

– If this bit is '1', the step changes depend on the STEP bit.

• DIR: When SPI_DIR = '1' -

– If DIR = '1', motor moves in the forward direction

– If DIR = '0', motor moves in the reverse direction.

• STEP: When SPI_STEP = '1' -

– If STEP = '1', the indexer advances by one step.

– STEP bit is self-clearing, it becomes '0' after writing '1' to it.

When operating with the SPI interface, depending on the STEP_EDGE bit, STEP active edge can be either

rising edge or both rising and falling edge, as shown in Table 7-9. When configured with H/W interface, the STEP

active edge is only the rising edge. For applications that need to run at high input STEP rate, configuring both

edges as active edge reduces controller overhead by half, because the input STEP rate is effectively doubled.

Table 7-9. STEP Active Edge

MODE

STEP_EDGE

STEP Active Edge

0b (default)

Rising edge

Rising edge and falling edge

Rising edge

At each active edge of the STEP input the indexer advances to the next state in the table. The direction shown is

with the DIR pin logic high. If the DIR pin is logic low, the sequence table is reversed.

After power-up, after exiting logic undervoltage lockout, or after exiting sleep mode, the indexer moves to an

initial excitation state (home position) of 45° electrical angle, corresponding to 71% of full-scale current in both

coils. All the registers are restored to their deafult values in such scenario.

Note

• The production samples will feature an INDEX_RESET bit located in CTRL1 register bit 5. This bit

will reset the indexer to 45° electrical angle, but the contents of the registers will not change. In

pre-production samples, this bit will be reserved.

• If the step mode is changed dynamically while stepping, the indexer advances to the next valid

state for the new step mode setting at the active edge of STEP.

If the STEP input frequency is jittery, the device filters the signal for the purpose of stall detection. The

FRQ_CHG and STEP_FRQ_TOL bits program the filter setting, as shown in Table 7-10. 2% filtering means

up to 2% jitter around the center frequency will be filtered out to generate a clean STEP signal for internal

circuits to detect motor stall.

Table 7-10. STEP frequency filtering

FRQ_CHG

STEP_FRQ_TOL

Filtering

0 (default)

01 (default)

Don't care

No filtering

7.4.5 Indexer Output

• A 10-bit INDEX_POS register indicates actual position in the microstep table for coil A current.

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DRV8452

SLOSE84 – AUGUST 2022

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DRV8452SPWPR Datasheet(PDF) 21 Page - Texas Instruments

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