OPA992 datasheet(10/70 Pages) TI

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6.7 Electrical Characteristics (continued)

For VS = (V+) – (V–) = 2.7 V to 40 V (±1.35 V to ±20 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT

= VS / 2, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

FREQUENCY RESPONSE

GBW

Gain-bandwidth product

10.6

MHz

Slew rate

VS = 40 V, G = +1, VSTEP = 10 V, CL = 20 pF(5)

V/μs

Settling time

To 0.1%, VS = 40 V, VSTEP = 10 V, G = +1, CL = 20 pF

0.65

μs

To 0.1%, VS = 40 V, VSTEP = 2 V, G = +1, CL = 20 pF

0.3

To 0.01%, VS = 40 V, VSTEP = 10 V, G = +1, CL = 20 pF

0.86

To 0.01%, VS = 40 V, VSTEP = 2 V, G = +1, CL = 20 pF

0.44

Phase margin

G = +1, RL = 10 kΩ, CL = 20 pF

Overload recovery time

VIN × gain > VS

170

THD+N

Total harmonic distortion +

noise

VS = 40 V, VO = 3 VRMS, G = 1, f = 1 kHz, RL = 10 kΩ

0.00005%

126

VS = 10 V, VO = 3 VRMS, G = 1, f = 1 kHz, RL = 128 Ω

0.0032%

VS = 10 V, VO = 0.4 VRMS, G = 1, f = 1 kHz, RL = 32 Ω

0.00032%

110

OUTPUT

Voltage output swing from

rail

Positive and negative

rail headroom

VS = 40 V, RL = no load

VS = 40 V, RL = 10 kΩ

VS = 40 V, RL = 2 kΩ

220

300

VS = 2.7 V, RL = no load

0.5

VS = 2.7 V, RL = 10 kΩ

VS = 2.7 V, RL = 2 kΩ

ISC

Short-circuit current

±65(3)

CLOAD

Capacitive load drive

See Phase Margin vs Capacitive Load

Open-loop output

impedance

IO = 0 A

See Open-Loop Output Impedance vs

Frequency

Ω

POWER SUPPLY

Quiescent current per

amplifier

OPA2992, OPA4992, IO = 0 A

2.4

2.8

TA = –40°C to 125°C

2.84

OPA992, IO = 0 A

2.48

2.92

TA = –40°C to 125°C

2.98

SHUTDOWN

IQSD

Quiescent current per

amplifier

VS = 2.7 V to 40 V, all amplifiers disabled, SHDN = V– + 2 V

µA

ZSHDN

Output impedance during

shutdown

VS = 2.7 V to 40 V, amplifier disabled

10 || 2

GΩ || pF

VIH

Logic high threshold

voltage (amplifier disabled)

For valid input high, the SHDN pin voltage should be greater

than the maximum threshold but less than or equal to V+ or

(V–) + 20 V, whichever is less

(V–) + 1.1 V

VIL

Logic low threshold

voltage (amplifier enabled)

For valid input low, the SHDN pin voltage should be less than

the minimum threshold but greater than or equal to V–

(V–) + 0.2

tON

Amplifier enable time (from

shutdown) (2)

VS = ±20 V, G = +1, VCM = VS / 2, RL = 10 kΩ connected to

V–

µs

tOFF

Amplifier disable time (2)

VS = ±20 V, G = +1, VCM = VS / 2, RL = 10 kΩ connected to

V–

µs

SHDN pin input bias

current (per pin)

VS = 2.7 V to 40 V, (V–) + 20 V (4) ≥ SHDN ≥ (V–) + 0.9 V

500

VS = 2.7 V to 40 V, (V–) ≤ SHDN ≤ (V–) + 0.7 V

400

(1)

Specified by characterization only.

(2)

Disable time (tOFF) and enable time (tON) are defined as the time interval between the 50% point of the signal applied to the SHDN pin

and the point at which the output voltage reaches 10% (disable) or 90% (enable) of its final value.

OPA992, OPA2992, OPA4992

SBOSA10D – JUNE 2021 – REVISED AUGUST 2022

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