NAND01G-B2C datasheet(30/67 Pages) NUMONYX

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Device operations

NAND01G-B2C

30/67

Figure 14.

Page copy back program with random data input

6.5

Block erase

Erase operations are done one block at a time. An erase operation sets all of the bits in the

addressed block to ‘1’. All previous data in the block is lost.

An erase operation consists of three steps (refer to Figure 15):

One bus cycle is required to setup the Block Erase command. Only addresses A18-

A27 (x8) or A17-A26 (x16) are used, the other address inputs are ignored

Two bus cycles are then required to load the address of the block to be erased. Refer to

Table 8 and Table 9 for the block addresses of each device

One bus cycle is required to issue the Block Erase Confirm command to start the P/E/R

controller.

The operation is initiated on the rising edge of write Enable, W, after the Confirm command

is issued. The P/E/R controller handles block erase and implements the verify process.

During the block erase operation, only the Read Status Register and Reset commands will

be accepted, all other commands will be ignored.

Once the program operation has completed the P/E/R controller bit SR6 is set to ‘1’ and the

Ready/Busy signal goes High. If the operation completed successfully, the write status bit

SR0 is ‘0’, otherwise it is set to ‘1’.

Figure 15.

Block erase operation

I/O

Source

Add Inputs

ai11001

85h

Read

Code

Target

Add Inputs

tBLBH1

(Read Busy time)

00h

Busy

35h

85h

Data

2 Cycle

Add Inputs

Data

Copy Back

Code

10h

70h

Unlimited number of repetitions

Busy

tBLBH2

(Program Busy time)

SR0

I/O

Block Address

Inputs

SR0

ai07593

D0h

70h

60h

Block Erase

Setup Code

Confirm

Code

Read Status Register

Busy

tBLBH3

(Erase Busy time)

NAND01G-B2C Datasheet(PDF) 30 Page - Numonyx B.V

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