HT46R52 datasheet(14/42 Pages) HOLTEK

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HT46R51/HT46R52

Rev. 1.40

July 12, 2005

Bit No.

Label

Function

PSC0

PSC1

PSC2

Defines the prescaler stages, PSC2, PSC1, PSC0=

000: fINT=fSYS

001: fINT=fSYS/2

010: fINT=fSYS/4

011: fINT=fSYS/8

100: fINT=fSYS/16

101: fINT=fSYS/32

110: fINT=fSYS/64

111: fINT=fSYS/128

3TE

Defines the TMR active edge of the timer/event counter:

In Event Counter Mode (TM1,TM0)=(0,1):

1:count on falling edge;

0:count on rising edge

In Pulse Width measurement mode (TM1,TM0)=(1,1):

1: start counting on the rising edge, stop on the falling edge;

0: start counting on the falling edge, stop on the rising edge

TON

Enable/disable timer counting (0=disable; 1=enable)

Unused bit, read as

²0²

TM0

TM1

Defines the operating mode, TM1, TM0:

01=Event count mode (external clock)

10=Timer mode (internal clock)

11=Pulse width measurement mode

00=Unused

TMRC (0EH) Register

Input/Output Ports

There are 14 bidirectional input/output lines in the

microcontroller, labeled as PA, PB and PD, which are

mapped to the data memory of [12H], [14H] and [18H]

respectively. All of these I/O ports can be used for input

and output operations. For input operation, these ports

are non-latching, that is, the inputs must be ready at the

T2 rising edge of instruction

²MOV A,[m]² (m=12H, 14H

or 18H). For output operation, all the data is latched and

remains unchanged until the output latch is rewritten.

Each I/O line has its own control register (PAC, PBC,

PDC) to control the input/output configuration. With this

control register, CMOS output or Schmitt trigger input

with or without pull-high resistor structures can be re-

configured dynamically under software control. To func-

tion as an input, the corresponding latch of the control

²1². The input source also depends

on the control register. If the control register bit is

²1²,

the input will read the pad state. If the control register bit

V D D

E N ( P F D o r P W M )

W a k e - u p

I N T f o r P A 5 O n l y

S y s t e m W a k e - u p

( P A o n l y )

R e a d D a t a R e g i s t e r

C K

C o n t r o l B i t

P U

D a t a B u s

W r i t e C o n t r o l R e g i s t e r

C h i p R e s e t

R e a d C o n t r o l R e g i s t e r

W r i t e D a t a R e g i s t e r

D a t a B i t

P A 0 ~ P A 2

P A 3 / P F D

P A 4 / T M R

P A 5 / I N T

P A 6

P A 7

P B 0 / A N 0 ~ P B 4 / A N 4

P D 0 / P W M

[ P A 3 , P F D ]

o r [ P D 0 , P W M ]

Input/Output Ports

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