HT46R51/HT46R52

Rev. 1.40

17

July 12, 2005

Bit No. Label

Function

0

1

2

ACS0

ACS1

ACS2

Defines the analog channel select

3

4

5

PCR0

PCR1

PCR2

Defines the port B configuration se-

lect. If PCR0, PCR1 and PCR2 are all

zero, the ADC circuit is powered off to

reduce power consumption

6

EOCB

Indicates end of A/D conversion.

(0= end of A/D conversion)

Each time bits 3~5 change state the

A/D should be initialised by issuing a

START signal, otherwise the EOCB

flag may have an undefined condition.

See

²Important note for A/D initialis-

ation

².

7

START

Starts the A/D conversion.

0

®1®0= Start

0

®1= Reset A/D converter and set

EOCB to

²1².

ADCR (22H) Register

ACS2

ACS1

ACS0

Analog Channel

000

AN0

001

AN1

010

AN2

011

AN3

100

AN4

101

*

110

*

111

*

Analog Input Channel Selection

Note: * undefined, cannot be used

Register

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

ADRL (20H) D3

D2

D1

D0

0000

ADRH (21H) D11 D10 D9

D8

D7

D6

D5

D4

Note:

D0~D11 is A/D conversion result data bit

LSB~MSB.

PCR2

PCR1

PCR0

43210

0

0

0

PB4

PB3

PB2

PB1

PB0

0

0

1

PB4

PB3

PB2

PB1

AN0

0

1

0

PB4

PB3

PB2

AN1

AN0

0

1

1

PB4

PB3

AN2

AN1

AN0

1

0

0

PB4

AN3

AN2

AN1

AN0

1

0

1

AN4

AN3

AN2

AN1

AN0

110

Undefined, cannot be used

111

Port B Configuration

A / D c o n v e r s i o n t i m e

A / D c o n v e r s i o n t i m e

A / D c o n v e r s i o n t i m e

0 0 0 B

0 0 0 B

1 0 0 B

0 1 0 B

S T A R T

E O C B

P C R 2 ~

P C R 0

A C S 2 ~

A C S 0

P o w e r - o n

R e s e t

E n d o f A / D

c o n v e r s i o n

1 : D e f i n e P B c o n f i g u r a t i o n

2 : S e l e c t a n a l o g c h a n n e l

N o t e :

S t a r t o f A / D

c o n v e r s i o n

R e s e t A / D

c o n v e r t e r

A / D s a m p l i n g t i m e

1 0 0 B

0 0 0 B

S t a r t o f A / D

c o n v e r s i o n

R e s e t A / D

c o n v e r t e r

0 0 0 B

1 . P B p o r t s e t u p a s I / O s

2 . A / D c o n v e r t e r i s p o w e r e d o f f

t o r e d u c e p o w e r c o n s u m p t i o n

1 0 1 B

0 0 1 B

S t a r t o f A / D

c o n v e r s i o n

R e s e t A / D

c o n v e r t e r

d o n ' t c a r e

E n d o f A / D

c o n v e r s i o n

E n d o f A / D

c o n v e r s i o n

M i n i m u m o n e i n s t r u c t i o n c y c l e n e e d e d , M a x i m u m t e n i n s t r u c t i o n c y c l e s a l l o w e d

A / D s a m p l i n g t i m e

A / D s a m p l i n g t i m e

A/D Conversion Timing