OUT

IN

SW

IN(ripple)

OUT

ESR

I

D 1 D

C

F

V

I

R

˜

˜

t

˜

˜

(15)

The recommended high-frequency input capacitance is 4.4 µF or higher. Ensure the input capacitor is a high-

quality X7S or X7R ceramic capacitor with sufficient voltage rating for CIN. Based on the voltage coefficient of

ceramic capacitors, choose a voltage rating preferably twice the maximum input voltage. Additionally, some bulk

capacitance can be required for large input loop inductance or long wire harnesses used in the system. This

capacitor provides parallel damping to the resonance associated with parasitic inductance of the supply lines

and high-Q ceramics. See the Power Supply Recommendations section for more detail.

9.2.2.7 Type 3 Ripple Network

A Type 3 ripple generation network uses an RC filter consisting of RA and CA across SW and VOUT to generate

a triangular ramp that is in phase with the inductor current. This triangular ramp is then AC-coupled into the

feedback node using capacitor CB as shown in Figure 9-1. Type 3 ripple injection is suited for applications where

low output voltage ripple is crucial.

Use Equation 16 and Equation 17 to calculate RA and CA to provide the required ripple amplitude at the FB pin.

A

SW

FB1

FB2

10

C

F

R

R

t

˜

(16)

For the feedback resistor RFBT = 453 kΩ and RFBB = 49.9 kΩ values shown in Figure 9-1, Equation 16 dictates a

minimum CA of 742 pF. In this design, a 3300-pF capacitance is chosen. This value is chosen to keep RA within

practical limits between 100 kΩ and 1 MΩ when using Equation 17.

Ra ×Ca≤ VINnom −VOUT ×tONnom 

20mV

(17)

Based on CA set at 3.3 nF, RA is calculated to be 453 kΩ to provide a 20-mV ripple voltage at FB. The general

recommendation for a Type 3 network is to calculate RA and CA to get 20 mV of ripple at typical operating

conditions. A smaller RA can need to be used to operate below nominal 48-V input. Ensure 12 mV of FB ripple or

more at the minimum input voltage design to ensure stability.

While the amplitude of the generated ripple does not affect the output voltage ripple, it impacts the output

regulation as it reflects as a DC error of approximately half the amplitude of the generated ripple. For example,

a converter circuit with Type 3 network that generates a 40-mV ripple voltage at the feedback node has

approximately 10-mV worse load regulation scaled up through the FB divider to VOUT than the same circuit that

generates a 20-mV ripple at FB. Use Equation 18 to calculate the coupling capacitance, CB.

t

˜

TR-settling

B

FB1

t

C

3 R

(18)

where

• tTR-settling is the desired load transient response settling time.

CB calculates to 56 pF based on a 75-µs settling time. This value avoids excessive coupling capacitor discharge

by the feedback resistors during sleep intervals when operating at light loads. To avoid capacitance fall-off with

DC bias, use a C0G or NP0 dielectric capacitor for CB.

LM5013

SNVSCB3 – OCTOBER 2022

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