S3076DI datasheet(2/18 Pages) ETC1

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S3076

MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT

October 23, 2000 / Revision A

S3076 OVERVIEW

The S3076 supports clock recovery for the OC-48,

Fibre Channel (2125 Mbps), OC-24, Gigabit

Ethernet, Fibre Channel (1062.5 Mbps), OC-12 or

OC-3 data rate with FEC capabilty up to 8 bytes per

255-byte block. Differential serial data is input to the

chip at the specified rate, and clock recovery is per-

formed on the incoming data stream. An external os-

cillator is required to minimize the PLL lock time, and

provide a stable output clock source in the absence of

serial input data. Retimed data and clock are output

from the S3076.

Figure 2. S3076 Functional Block Diagram

SERCLKOP/N

LOCKDET

SERDATOP/N

REFCLKP/N

TESTCLK

LCKREFN

SERDATIP/N

LOOP

FILTER

VCO

CLOCK

DIVIDER

PHASE DETECTOR

LOCK

DETECTOR

SDN

CAP 1,2

RATESEL[1:0]

REFSEL

TESTEN

RST

BYPASS

TESTOUT

REFCMP

Suggested Interface Devices

Sumitomo

OC-48 Optical Receiver

AMCC S3057

OC-48 Transceiver

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