CS42L92 datasheet(49/333 Pages) CIRRUS

49 / 333 page

DS1162F2

CS42L92

4.3 Digital Core

The CS42L92 digital core provides extensive mixing and processing capabilities for multiple signal paths. The

configuration is highly flexible and supports virtually every conceivable input/output connection between the available

processing blocks.

The digital core provides parametric equalization (EQ) functions, DRC, and low-/high-pass filters (LHPF).

The CS42L92 supports multiple signal paths through the digital core. Stereo full-duplex sample-rate conversion is provided

to allow digital audio to be routed between input (ADC) paths, output (DAC) paths, digital audio interfaces (AIF1–AIF3)

and SLIMbus paths operating at different sample rates or referenced to asynchronous clock domains. Data-format

conversion (DFC) functions are available to support different interface standards on the input and output signal paths.

The integrated DSP provides a general-purpose signal processing capability; this is supported by general-purpose timer

and event-logger functions. Note that the DSP configuration data is lost whenever the DCVDD power domain is removed;

the DSP configuration data must be downloaded to the CS42L92 each time the device is powered up.

The digital core incorporates a S/PDIF transmitter that can provide a stereo S/PDIF output on a GPIO pin. Standard

sample rates of 32–192 kHz can be supported. The CS42L92 incorporates a tone generator that can be used for beep

functions through any of the audio signal paths. A white-noise generator is incorporated, to provide comfort noise in cases

where silence (digital mute) is not desirable.

A haptic signal generator is provided, for use with external haptic devices (e.g., mechanical vibration actuators). Two

pulse-width modulation (PWM) signal generators are also provided; the PWM waveforms can be modulated by an audio

source within the digital core and can be output on a GPIO pin.

An overview of the digital-core mixing and signal-processing functions is provided in Fig. 4-15. The control registers

associated with the digital-core signal paths are shown in Fig. 4-16 through Fig. 4-33. The full list of digital mixer control

registers (R1600–R3576) is provided in Section 6. Generic register field definitions are provided in Table 4-11.

The digital audio core is predominantly a 24-bit architecture, but also provides support for 32-bit signal paths. Audio data

samples of up to 32 bits can be received via the AIF1, AIF3, and SLIMbus input channels and routed to the AIF1, AIF3,

SLIMbus, S/PDIF, and DAC output paths. The respective output mixers provide full support for 32-bit data words.

Note that all other signal paths and signal-processing blocks within the digital core are limited to 24-bit data length; data

samples are truncated to 24-bit length if they are routed through any function that does not support 32-bit data words.

CS42L92 Datasheet(PDF) 49 Page - Cirrus Logic