CS42L92 datasheet(87/333 Pages) CIRRUS

87 / 333 page

DS1162F2

CS42L92

4.3 Digital Core

4.3.15 Asynchronous Sample-Rate Converter (ASRC)

The CS42L92 supports multiple signal paths through the digital core. Two independent clock domains are supported for

the audio signal paths, referenced to SYSCLK and ASYNCCLK respectively, as described in Section 4.16. Every digital

signal path must be synchronized either to SYSCLK or to ASYNCCLK.

The ASRC provides stereo, two-way signal paths between two sample rates, as shown in Fig. 4-32. Each of the sample

rates may be referenced to the SYSCLK or ASYNCCLK domain. The clock domains and sample rates associated with the

ASRC signal paths are selected using the ASRC1_RATE1 and ASRC1_RATE2 fields.

• ASRC1_RATE1 selects the clock domain and sample rate of the inputs to the ASRC1 IN1x paths, and the outputs

from the ASRC1 IN2x paths.

• ASRC1_RATE2 selects the clock domain and sample rate of the inputs to the ASRC1 IN2x paths, and the outputs

from the ASRC1 IN1x paths.

Note that it is possible to select two sample rates for the ASRC that are each referenced to the same clock domain. This

provides flexibility to switch between synchronous and asynchronous use cases without changing the signal routing

configuration of the affected audio paths.

See Section 4.16 for details of the sample-rate control registers.

The ASRC supports sample rates from 8–192 kHz. The ratio of the applicable SAMPLE_RATE_n and ASYNC_SAMPLE_

RATE_n fields must not exceed 6.

The ASRC1_RATE1 and ASRC1_RATE2 fields must not be changed if any of the respective x_SRCn fields is nonzero.

The associated x_SRCn fields must be cleared before writing new values to ASRC1_RATE1 or ASRC1_RATE2. A

minimum delay of 125

s must be allowed between clearing the x_SRCn fields and writing to the associated ASRC1_

RATE1 or ASRC1_RATE2 fields. See Table 4-27 for details.

R5248 (0x1480)

DFC1_CTRL_W0

6:2

DFC1_RATE[4:0]

0x00

DFCn Sample Rate

0x00 = SAMPLE_RATE_1

0x01 = SAMPLE_RATE_2

0x02 = SAMPLE_RATE_3

0x08 = ASYNC_SAMPLE_RATE_1

0x09 = ASYNC_SAMPLE_RATE_2

All other codes are reserved.

The selected sample rate is valid in the range 8–192 kHz.

The DFCn_SRC field must be cleared before changing DFCn_RATE.

R5254 (0x1486)

DFC2_CTRL_W0

6:2

DFC2_RATE[4:0]

0x00

R5260 (0x148C)

DFC3_CTRL_W0

6:2

DFC3_RATE[4:0]

0x00

R5266 (0x1492)

DFC4_CTRL_W0

6:2

DFC4_RATE[4:0]

0x00

R5272 (0x1498)

DFC5_CTRL_W0

6:2

DFC5_RATE[4:0]

0x00

R5278 (0x149E)

DFC6_CTRL_W0

6:2

DFC6_RATE[4:0]

0x00

R5284 (0x14A4)

DFC7_CTRL_W0

6:2

DFC7_RATE[4:0]

0x00

R5290 (0x14AA)

DFC8_CTRL_W0

6:2

DFC8_RATE[4:0]

0x00

R1048064 (0xF_

FE00)

DSP1_Config_1

15:11 DSP1_RATE[4:0]

0x00

DSP1 Sample Rate

0x00 = SAMPLE_RATE_1

0x01 = SAMPLE_RATE_2

0x02 = SAMPLE_RATE_3

0x08 = ASYNC_SAMPLE_RATE_1

0x09 = ASYNC_SAMPLE_RATE_2

All other codes are reserved.

The selected sample rate is valid in the range 8–384 kHz.

All DSP1xMIX_SRCm fields must be cleared before changing DSP1_RATE.

Table 4-26. Digital-Core Sample-Rate Control (Cont.)

Bit

Label

Default

Description

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