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CS42L92 Datasheet(PDF) 82 Page - Cirrus Logic |
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CS42L92 Datasheet(HTML) 82 Page - Cirrus Logic |
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82 / 333 page  82 DS1162F2 CS42L92 4.3 Digital Core Figure 4-31. Digital-Core Sample-Rate Control The input signal paths may be selected as input to the digital mixers or signal-processing functions. The sample rate for the input signal paths can either be set globally (using IN_RATE), or can be configured independently for each input channel (using the respective INnx_RATE fields). The applicable mode depends on IN_RATE_MODE, as described in FX_RATE + (GPIO pin) PWM PWM1 PWM2 (GPIO pin) S/PDIF PWM_RATE SPD1_RATE Tone Generator 1 Tone Generator Tone Generator 2 TONE_RATE Noise Generator White Noise Generator NOISE_GEN_RATE HAP_RATE Haptic Output Haptic Signal Generator SLIMRXn_RATE (n = 1..8) SLIMTXn_RATE (n = 1..8) + EQn EQ EQ1 EQ2 EQ3 EQ4 + LHPFn LHPF LHPF1 LHPF2 LHPF3 LHPF4 DRCn Left DRCn Right DRC DRC1 DRC2 + + OUT_RATE OUT_RATE IN_RATE, or INnx_RATE ASRC1_RATE1 ASRC1_RATE2 DFCn DFC DFC1 – DFC1_RATE DFC2 – DFC2_RATE DFC3 – DFC3_RATE DFC4 – DFC4_RATE DFCn DFC DFC5 – DFC5_RATE DFC6 – DFC6_RATE DFC7 – DFC7_RATE DFC8 – DFC8_RATE ASRC1 Left ASRC1 Right Asynchronous Sample Rate Converter (ASRC) ASRC1 ASRC1 Right ASRC1 Left ISRCn_FSL ISRCn_FSH ISRCn DEC1 ISRCn DEC2 ISRC2 Isochronous Sample Rate Converter (ISRC) ISRC1 ISRCn INT2 ISRCn INT1 SLIMbus SLIMbus = 8 input, 8 output + AIFn TX1 output + AIFn TX2 output + AIFn TX... output + AIFn TX... output AIFn RX... AIFn RX... AIFn RX2 AIFn RX1 etc... AIF1 = 8 input, 8 output AIF2 = 8 input, 8 output AIF3 = 8 input, 8 output AIF2 – AIF2_RATE AIF3 – AIF3_RATE AIF1 – AIF1_RATE DSP1 Ch 1 DSP1 Ch 2 DSP1 Ch 3 DSP1 Ch 4 DSP1 Ch 5 DSP1 Ch 6 DSP Core + + DSP1 – DSP1_RATE OUT5 OUT3 OUT2 + OUTnL output + OUTnR output Stereo Output Paths OUT1 IN1L signal path IN1R signal path IN2L signal path IN2R signal path IN3L signal path IN3R signal path IN4L signal path IN4R signal path US1_RATE US2_RATE Silence (mute) Ultrasonic 1 path AEC1 Loopback AEC2 Loopback Ultrasonic 2 path |
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