VD6283TX datasheet(9/59 Pages) STMICROELECTRONICS

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3.4

I2C interface

3.4.1

I2C protocol description

Device control and data transfer is performed through an I2C serial communication interface. The I2C interface

uses two signals: the serial data line (SDA) and serial clock line (SCL). Each device connected to the bus uses a

unique address and a simple master/slave relationship exists.

Both SDA and SCL lines are connected to a positive supply voltage using pull up resistors located on the host.

Lines are only active when driven low. When no data is transmitted both lines are high.

Clock signal (SCL) generation is performed by the master device. The master device initiates data transfer. The

I2C bus on the VD6283 has a maximum speed of 1 Mbit/s and the device supports a slave address of 0x40 (or

0x20 in 7 bits).

Figure 7. Data transfer protocol

Ac/Am

Start condition

Stop condition

SDA

SCL

Acknowledge

Addressor data byte

MSB

LSB

Information is exchanged in 8 bit packets (bytes) always followed by an acknowledge bit, Ac for VD6283

acknowledge and Am for master acknowledge (host bus master). The internal data are produced by sampling

SDA at a rising edge of SCL. The external data must be stable during the high period of SCL. The exceptions to

this are start (S) or stop (P) conditions when SDA falls or rises respectively, while SCL is high.

An I2C message contains a series of bytes preceded by a start condition and followed by either a stop or

repeated start (another start condition but without a preceding stop condition) followed by another message. The

first byte contains the device address and also specifies the data direction. If the least significant bit is low (that is,

0x40) the message is a master write command to the slave. If the LSB is set (that is, 0x41) then the message is a

master read command from the slave.

Figure 8. I2C device address

MSBit

LSBit

R/W

All serial interface communications with the ambient light sensor must begin with a start condition. The sensor

acknowledges reception of a valid address by driving the SDA line low. The state of the read/write bit (LSB of the

address byte) is stored and the next byte of data, sampled from SDA, can be interpreted. During a write sequence

the second byte received provides an 8 bit index which points to one of the internal 8 bit registers.

Figure 9. Data format (write)

VD628x acknowledges

Ac P

valid address

VD628x

Acknowledge from

ADDRESS [7:0]

INDEX[7:0]

DATA[7:0]

0x40 (write)

Start

Stop

As data are received by the slave, they are written bit by bit to a serial/parallel register. After each data byte

has been received by the slave, an acknowledge is generated, the data are then stored in the internal register

addressed by the current index.

During a read message, the contents of the register addressed by the current index are read out in the byte

following the device address byte. The contents of this register are parallel loaded into the serial/parallel register

and clocked out of the device by the falling edge of SCL.

VD6283TX

I2C interface

DS13735 - Rev 1

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