LT4294 datasheet(18/30 Pages) AD

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Figure 11. Type 1 or 2 PSE, 1-Event Class Sequence

LTC9101-3/LTC9103

Rev. 0

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APPLICATIONS INFORMATION

91013 F12

VCLASSMIN

VMARKMAX

VSIGMIN

VRESET

DETECT

1ST

CLASS

1ST

MARK

2ND

MARK

2ND

CLASS

POWER ON

Figure 12. Type 2 PSE, 2-Event Class Sequence

91013 F11

VCLASSMIN

VMARKMAX

VSIGMIN

VRESET

DETECT

CLASS

POWER ON

The concept of demotion is introduced in 802.3at. A

Type 2 PD may be connected to a PSE only capable of

delivering 13W, perhaps due to power management lim-

itations. In this case, the PSE will perform a single classi-

fication event as shown in Figure 11, and note that 25.5W

is requested. Due to the limited power availability, the

PSE will not issue a second event and proceeds directly

to power on the PD. The presence of a single class event

informs the Type 2 PD it has been demoted to 13W. If

demoted, the PD is subject to power limitations and may

operate in a reduced power mode.

Invalid Type 2 Class Combinations

The 802.3at specification defines a Type 2 PD class signa-

ture as two consecutive Class 4 results; a Class 4 followed

by a Class 0-3 is not a valid signature. The LTC9101-3/

LTC9103 will not provide power to a PD with an invalid

class signature.

POWER CONTROL

The primary function of the LTC9101-3/LTC9103 is to

control power delivery to the PSE port. It does this by

controlling the gate drive voltage of an external power

MOSFET while monitoring the current (through an exter-

nal sense resistor) and the output voltage (across the

OUT pin).

The LTC9101-3/LTC9103 connects the VEE power sup-

ply to the PSE port in a controlled manner, meeting the

power demands of the PD while minimizing power dis-

sipation in the external MOSFET and disturbances to the

VEE backplane.

Inrush Control

When commanded to apply power to a port, the

LTC9101-3/LTC9103 ramps up the GATE pin, raising the

external MOSFET gate voltage in a controlled manner.

During a typical inrush, the MOSFET gate voltage will rise

until the external MOSFET is fully enhanced or the port

reaches the inrush current limit (IINRUSH). IINRUSH is set

automatically by the PSE. The GATE pin will be servoed

if port current exceeds IINRUSH, actively limiting current

to IINRUSH. When the GATE pin is not being servoed, the

final VGS is 12V (typical).

During inrush, the port runs a timer (tSTART). The port

stays in inrush until tSTART expires. When tSTART expires,

the PSE inspects port voltage and current. When the PSE

is applying power to a PD, inrush is successful if the port is

drawing current below IINRUSH. If inrush is not successful,

power is removed and a tSTART fault is set. Otherwise, the

port advances to power on and the programmed current

limiting thresholds are used as described in the Current

Cutoff and Limit section.

Port Power Policing

The power policing threshold (PCUT) is monitored on a

per-port basis per Table 4. When the total output power

over 100ms moving average exceeds the specified thresh-

old, power is removed from the port.

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