SigmaTel, Inc.
Data Sheet
STAC9721
13
04/07/00
04/07/00
Figure 6. Start of an Audio Output Frame
SYNC
BIT_CLK
SDATA_OUT
first SDATA_OUT bit of frame here
SYNC assertion here
valid
Frame
slot1
slot2
End of previous audio frame
SDATA_OUT’s composite stream is MSB justified (MSB first) with all non-valid slots’
bit positions stuffed with 0’s by the AC'97 controller.
.
When mono audio sample streams are sent from the AC'97 controller it is necessary that
BOTH left and right sample stream time slots be filled with the same data.
3.1.1.1
Slot 1: Command Address Port
The command port is used to control features, and monitor status (see Audio Input Frame
Slots 1 and 2) of the STAC9721/23 functions including, but not limited to, mixer
settings, and power management (refer to the control register section of this
specification).
The control interface architecture supports up to 64 16-bit read/write registers,
addressable on even byte boundaries. Only the even registers (00h, 02h, etc.) are valid.
Audio output frame slot 1 communicates control register address, and write/read
command information to the STAC9721/23.
Command Address Port bit assignments:
Bit (19) Read/Write command (1= read, 0=write)
Bit (18:12)
Control Register Index (64 16-bit locations, addressed on even byte
boundaries)
Bit (11:0)
Reserved (Stuffed with 0's)
The first bit (MSB) sampled by STAC9721/23 indicates whether the current control
transaction is a read or a write operation. The following 7 bit positions communicate the
targeted control register address. The trailing 12 bit positions within the slot are reserved
and must he stuffed with 0's by the AC'97 controller.
3.1.1.2
Slot 2: Command Data Port
The command data port is used to deliver 16-bit control register write data in the event
that the current command port operation is a write cycle. (as indicated by Slot 1, bit 19)
Bit (19:4)
Control Register Write Data
(Stuffed with 0's if current operation is a
read)
Bit (3 :0)
Reserved
(Stuffed with 0's)
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