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SigmaTel, Inc.
Data Sheet
STAC9721
34
04/07/00
04/07/00
9.2 Warm Reset
Figure 14. Warm Reset
SYNC
BIT_CLK
Tsync_2clk
Tsync_high
Table 24. Warm Reset
Parameter
Symbol
Min
Typ
Max
Units
SYNC active high pulse width
Tsync_high
1.0
1.3
-
us
SYNC inactive to BIT_CLK startup delay
Tsync2clk
162.8
-
-
ns
9.3 Clocks
Figure 15. Clocks
BIT_CLK
SYNC
Tclk_high
Tclk_low
Tclk_period
Tsync_low
Tsync_high
Tsync_period
Table 25. Clocks
Parameter
Symbol
Min
Typ
Max
Units
BIT_CLK frequency
-
12.288
-
MHz
BIT_CLK period
Tclk_period
-
81.4
-
ns
BIT_CLK output jitter
-
-
750
ps
BLT_CLK high pulsewidth (note 1)
Tclk_high
36
40.7
45
ns
BIT_CLK low pulse width (note 1)
Tclk_low
36
40.7
45
ns
SYNC frequency
-
48.0
-
kHz
SYNC period
Tsync_period
-
20.8
-
us
SYNC high pulse width
Tsync_high
-
1.3
-
us
SYNC low_pulse width
Tsync_low
-
19.5
-
us
Notes: 1) Worst case duty cycle restricted to 40/60.
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