VS8053 datasheet(17/79 Pages) VLSI

17 / 79 page

VS8053b Datasheet

SPI BUSES

7.2

Data Request Pin DREQ

The DREQ pin/signal is used to signal if VS8053b’s 2048-byte FIFO is capable of receiving

data. If DREQ is high, VS8053b can take at least 32 bytes of SDI data or one SCI command.

DREQ is turned low when the stream buffer is too full and for the duration of an SCI command.

Because of the 32-byte safety area, the sender may send up to 32 bytes of SDI data at a

time without checking the status of DREQ, making controlling VS8053b easier for low-speed

microcontrollers.

Note: DREQ may turn low or high at any time, even during a byte transmission. Thus, DREQ

should only be used to decide whether to send more bytes. A transmission that has already

started doesn’t need to be aborted.

Note: In VS8053b DREQ also goes down while an SCI operation is in progress.

There are cases when you still want to send SCI commands when DREQ is low. Because

DREQ is shared between SDI and SCI, you can not determine if an SCI command has been

executed if SDI is not ready to receive data. In this case you need a long enough delay after

every SCI command to make certain none of them are missed. The SCI Registers table in

Chapter 9.6 gives the worst-case handling time for each SCI register write.

Note: The status of DREQ can also be read through SCI with the following code. For details on

SCI registers, see Chapter 7.4.

// This example reads status of DREQ pin through the SPI/SCI register

// interface.

#define SCI_WRAMADDR 7

#define SCI_WRAM 6

while (!endOfFile) {

int dreq;

WriteSciReg(SCI_WRAMADDR, 0xC012); // Send address of DREQ register

dreq = ReadSciReg(SCI_WRAM) & 1;

// Read value of DREQ (in bit 0)

if (dreq) {

// DREQ high: send 1-32 bytes audio data

} else {

// DREQ low: wait 5 milliseconds (so that VS10xx doesn't get

// continuous SCI operations)

}

} /* while (!endOfFile) */

Version: 1.31, 2017-11-17

VS8053 Datasheet(PDF) 17 Page - VLSI Solution Oy