198

12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012

12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012

PS8142A 10/13/98

PI6C100

Precision Clock Synthesizer

for Desktop PC’s

REF0

1

REF1

2

XTAL_IN

4

XTAL_OUT

5

6

PCICLK_F

7

PCICLK1

8

9

PCICLK2

10

PCICLK3

11

PCICLK4

13

PCICLK5

14

PCICLK6

16

PCICLK7

17

19

20

48MHz

22

48MHz

23

REF2

APIC0

APIC1

NC

CPUCLK0

48

CPUCLK1

47

46

45

CPUCLK2

44

CPUCLK3

43

42

41

40

PCISTOP#

39

CPUSTOP#

38

PWRDWN#

37

SPREAD#

36

SEL0

35

SEL1

34

SEL100/66#

33

32

31

30

29

28

27

26

25

PinConfiguration

Block Diagram

Features

• 100 MHz or 66 MHz operation

• Eight copies of PCI clock, (synchronous with CPU clock) 3.3V

• Two copies of IO APIC clock @14.31818 MHz

• Two copies of 48 MHz clock

• ThreecopiesofRef.clock@14.31818MHz(3.3VTTL)

• Low cost 14.31818 MHz crystal oscillator input

• Spread spectrum modulation of CPU and PCI clocks for

reduced EMI

• Power management control

• 48-pinSSOPpackage(V48)

Description

The PI6C100 is a high-speed low-noise clock generator designed to

work with the PI6C180 clock buffer to meet all clock needs for Intel

Architecture platforms. CPU and chipset clock frequencies of 66.6

MHz and 100 MHz are supported.

Split supplies of 3.3V and 2.5V are used. The 3.3V power supply

powers a portion of the I/O and the core. The 2.5V is used to power

the remaining outputs. 2.5V signaling follows JEDEC standard

8-X.Powersequencingofthe3.3Vand2.5Vsuppliesisnotrequired.

An asynchronous PWRDWN# signal may be used to orderly power

down (or up) the system.

48-Pin

V48

PCICLK[1:7]

CPUCLK[0:3]

REF[0:2]

3

APIC0,1

REF

OSC

CPUSTOP#

4

7

PCICLK_F

PCISTOP#

÷2

PLL1

2 48MHz

PLL2

SEL0,1

SPREAD#

XTAL_OUT

XTAL_IN

*KBBAHI

2

SEL100/66#