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PS8142A 10/13/98

PI6C100

Precision Clock Synthesizer

for Desktop PC’s

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Minimum and Maximum Expected Capacitive Loads

Notes:

1. Maximum rise/fall times are guaranteed at maximum specified load for each type of output buffer.

2. Minimum rise/fall times are guaranteed at minimum specified load for each type of output buffer.

3. Rise/fall times are specified with pure capacitive load as shown. Testing is done with an

additional 500W resistor in parallel.

Design Guidelines to Reduce EMI

1. Place series resistors and CI capacitors as close as possible to the respective clock pins. Typical value for

CI is 10pF. Series resistor value can be increased to reduce EMI provided that the rise and fall time are still

within the specified values.

2. Minimize the number of “vias” of the clock traces.

3. Route clock traces over a continuous ground plane or over a continuous power plane. Avoid routing clock

traces from plane to plane (refer to rule #2).

4. Position clock signals away from signals that go to any cables or any external connectors.

CPUCLK

PCICLK

REF

APIC

48MHZ

33Ω

33Ω

22Ω/33Ω

33Ω

22Ω

4

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3

2

2

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CL

CL

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21$+

1 Device load

Meets PCI2.1 Req.

1 Device load

2 Device loads

1 Device load