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MAX9322 Datasheet(PDF) 4 Page - Maxim Integrated Products

Part # MAX9322
Description  LVECL/LVPECL 1:15 Differential Divide-by-1/Divide-by-2 Clock Driver
PDF  13 Pages
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Manufacturer  MAXIM [Maxim Integrated Products]
Direct Link  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

MAX9322 Datasheet(HTML) 4 Page - Maxim Integrated Products

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LVECL/LVPECL 1:15 Differential
Divide-by-1/Divide-by-2 Clock Driver
4
_______________________________________________________________________________________
Note 1: Measurements are made with the device in thermal equilibrium.
Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative.
Note 3: Single-ended CLK_, CLK_ input operation is limited to VCC - VEE = 3.0V to 3.8V.
Note 4: DC parameters are production tested at TA = +25°C and guaranteed by design over the full operating temperature range.
Note 5: Use VBB as a reference for inputs of the same device only.
Note 6: All pins open except VCC and VEE.
Note 7: Guaranteed by design and characterization. Limits are set at ±6 sigma.
Note 8: Measured between outputs of the same parts at the signal crossing points under identical conditions for a same-edge transition.
Note 9: Device jitter added to a jitter-free input signal.
AC ELECTRICAL CHARACTERISTICS
((VCC - VEE) = 2.375V to 3.8V; outputs loaded with 50
Ω ±1% to VCC - 2V; input frequency ≤ 1000MHz; input transition time = 125ps
(20% to 80%); CLK_SEL, FSEL_ = high or low, MR = low; VIHD = VEE + 1.2V to VCC; VILD = VEE to VCC - 0.4V; VIHD - VILD = 0.4V to
1V. Typical values are at (VCC - VEE) = 3.3V, VIHD = VCC - 1V, VILD = VCC - 1.5V.) (Note 7)
-40
°C
+25
°C
+85
°C
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Differential Input-to-
Output Delay
tPLHD,
tPHLD
Figure 2
700
900
1150
725
900
1180
750
950
1225
ps
Single-Ended
CLK_/CLK_ to
Output Delay
tPHLS,
tPLHS
Figure 1
700
900
1170
700
900
1175
725
950
1250
ps
MR to Output
Delay
tPD
Figure 3
450
930
450
930
450
930
ps
Output-to-Output
Skew
tSKOO
(Note 8)
85
56
50
ps
Added Random
Jitter
tRJ
fIN = 1.0GHz
clock pattern
(Note 9)
1.2
1.2
1.2
ps
(RMS)
Added
Deterministic Jitter
tDJ
1Gbps 223 - 1
PRBS pattern
(Note 9)
61
61
61
psP-P
Switching
Frequency
fMAX
VOD > 300mV
1.0
1.0
1.0
GHz
Differential Output
Rise and Fall Time
(20% to 80%)
tR, tF
Figure 2
200
260
400
200
260
400
200
240
400
ps



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