MAX9322 datasheet(6/13 Pages) MAXIM

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LVECL/LVPECL 1:15 Differential

Divide-by-1/Divide-by-2 Clock Driver

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Pin Description

TQFP

QFN

NAME

FUNCTION

2, 3

VCC

Positive Power Supply. Powers input circuitry. Bypass each VCC to VEE with a 0.01µF

and 0.1µF capacitor. Place the capacitors as close to the device as possible with the

smaller value capacitor closest to the device.

Single-Ended Master Reset. A high on MR sets all outputs to differential zero. A low on

MR enables all outputs. MR is pulled to VEE through a 75k

Ω resistor.

FSELA

Single-Ended Frequency Select A. Selects the output frequency for bank A. Bank A

consists of two differential outputs. A low on FSELA selects divide-by-1. A high on

FSELA selects divide-by-2. FSELA is pulled to VEE through a 75k

Ω resistor.

FSELB

Single-Ended Frequency Select B. Selects the output frequency for bank B. Bank B

consists of three differential outputs. A low on FSELB selects divide-by-1. A high on

FSELB selects divide-by-2. FSELB is pulled to VEE through a 75k

Ω resistor.

CLK0

Noninverting Clock 0 Input. CLK0 is pulled to VEE through 75k

Ω resistors.

CLK0

Inverting Clock 0 Input. CLK0 is pulled to VCC and to VEE through a 75k

Ω resistor.

CLK_SEL

Single-Ended Clock Selector Input. A low on CLK_SEL selects CLK0. A high on

CLK_SEL selects CLK1. CLK_SEL is pulled to VEE through a 75k

Ω resistor.

CLK1

Noninverting Clock 1 Input. CLK1 is pulled to VEE through a 75k

Ω resistor.

911

CLK1

Inverting Clock 1 Input. CLK1 is pulled to VCC and to VEE through 75k

Ω resistors.

VBB

Reference Voltage Output. Connect VBB to CLK_ or CLK_ to provide a reference for

single-ended operation. When used, bypass with a 0.01µF ceramic capacitor to VCC;

otherwise leave open.

FSELC

Single-Ended Frequency Select C. Selects the output frequency for bank C. Bank C

consists of four differential outputs. A low on FSELC selects divide-by-1. A high on

FSELC selects divide-by-2. FSELC is pulled to VEE through a 75k

Ω resistor.

FSELD

Single-Ended Frequency Select D. Selects the output frequency for bank D. Bank D

consists of six differential outputs. A low on FSELD selects divide-by-1. A high on

FSELD selects divide-by-2. FSELD is pulled to VEE through a 75k

Ω resistor.

15, 16

VEE

Negative Power-Supply Input

14, 27, 30,

39, 40, 47,

19, 20, 33,

36, 37, 40,

49, 50, 53,

54, 61, 66, 67

VCCO

Output Driver Positive Power Supply. Powers device output drivers. Bypass each VCCO

to VEE with a 0.01µF and 0.1µF capacitor. Place the capacitors as close to the device

as possible with the smaller value capacitor closest to the device.

QD5

Inverting QD5 Output. Typically terminate with 50

Ω resistor to VCC - 2V.

QD5

Noninverting QD5 Output. Typically terminate with 50

Ω resistor to VCC - 2V.

QD4

Inverting QD4 Output. Typically terminate with 50

Ω resistor to VCC - 2V.

QD4

Noninverting QD4 Output. Typically terminate with 50

Ω resistor to VCC - 2V.

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