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TMUX7348F Datasheet(PDF) 4 Page - Texas Instruments |
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TMUX7348F Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 60 page ![]() Table 6-1. Pin Functions: TMUX7348F (continued) PIN TYPE(1) DESCRIPTION NAME TSSOP WQFN VDD 17 15 P Positive power supply. This pin is the most positive power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND. VFN 9 7 P Negative fault voltage supply that determines the overvoltage protection triggering threshold on the negative side. Connect to VSS if the triggering threshold will be the same as the device's negative supply. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VFN and GND. VFP 12 10 P Positive fault voltage supply that determines the overvoltage protection triggering threshold on the positive side. Connect to VDD if the triggering threshold will be the same as the device's positive supply. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VFP and GND. VSS 3 1 P Negative power supply. This pin is the most negative power-supply potential. In single-supply applications, this pin can be connected to ground. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VSS and GND. Thermal Pad — Thermal pad. The thermal pad is not connected internally. It is recommended that the pad be tied to GND or VSS for best performance. (1) I = input, O = output, I/O = input and output, P = power 1 A0 20 A1 2 EN 19 GND 3 VSS 18 VDD 4 S1A 17 S1B 5 S2A 16 S2B 6 S3A 15 S3B 7 S4A 14 S4B 8 DA 13 DB 9 VFN 12 VFP 10 SF 11 FF Not to scale Figure 6-3. PW Package, 20-Pin TSSOP (Top View) 1 VSS 15 S1B 2 S1A 14 S2B 3 S2A 13 S3B 4 S3A 12 S4B 5 S4A 11 DB Not to scale Thermal Pad Figure 6-4. RTJ Package, 20-Pin WQFN (Top View) Table 6-2. Pin Functions: TMUX7349F PIN TYPE(1) DESCRIPTION NAME TSSOP WQFN A0 1 19 I Logic control input address 0 (A0). The pin has a 4-MΩ internal pull-down resistor. This pin can also be used together with the specific fault pin (SF) to indicate which input is under fault. For more details, see Section 9.4.3. A1 20 18 I Logic control input address 1 (A1). The pin has a 4-MΩ internal pull-down resistor. This pin can also be used together with the specific fault pin (SF) to indicate which input is under fault. For more details, see Section 9.4.3. DA 8 6 I/O Drain terminal A. Can be an input or output. The drain pin is not overvoltage protected and shall remain within the recommended operating range. DB 13 11 I/O Drain terminal B. Can be an input or output. The drain pin is not overvoltage protected and shall remain within the recommended operating range. EN 2 20 I Active high logic enable (EN) pin. The pin has a 4-MΩ internal pull-down resistor. The device is disabled and all switches become high impedance when the pin is low. When the pin is high, the Ax logic inputs determine individual switch states. This pin can also be used together with the specific fault pin (SF) to indicate which input is under fault. For more details, see Section 9.4.3. FF 11 9 O General fault flag. This pin is an open drain output and is asserted low when overvoltage condition is detected on any of the source (Sx) input pins. Connect this pin to an external supply (1.8 V to 5.5 V) through a 1-kΩ pull-up resistor. GND 19 17 P Ground (0 V) reference S1A 4 2 I/O Overvoltage protected source pin 1A. Can be an input or output. S1B 17 15 I/O Overvoltage protected source pin 1B. Can be an input or output. TMUX7348F, TMUX7349F SCDS400A – MARCH 2022 – REVISED NOVEMBER 2022 www.ti.com 4 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMUX7348F TMUX7349F |
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