AP22980

Document number: DS45227 Rev. 2 - 2

11 of 14

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September 2022

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AP22980

Application Information

ENABLE/DISABLE CONTROL

The EN pin controls the state of the power switch. AP22980 is enabled when the EN pin is asserted high and the device is disabled when EN pin

is asserted low. The EN input is compatible with both TTL and CMOS logic. This pin cannot be left floating and must be tied either high or low for

proper functionality.

INPUT CAPACITOR

To limit the voltage drop on the input supply when the switch turns on into a discharged load capacitor resulting in a transient inrush current, a

capacitor needs to be placed between VIN and GND. Use 1

μF capacitor or a larger value for high-current applications. Place the capacitor close

to the VIN pins.

OUTPUT CAPACITOR

The recommended output capacitor value is 0.1

μF when switching lighter load. For heavier loads close to 6A, it is recommended that the VIN and

VOUT trace lengths need to be

a minimum. In addition, a bulk capacitor (≥ 10μF) may also be placed close to the VOUT pin. If using a bulk

capacitor on VOUT, it is important to control the inrush current by choosing an appropriate soft-start time in order to minimize the droop on the

input supply.

TRI-STATE SOFT-START TIME

Soft-start slew rate can be set by tri-state input with SS pin. The tri-state SS pin status is latched upon initial power up when VBIAS becomes valid

state and the first EN pin goes high, so it is recommended to set SS pin state prior to valid VBIAS and EN goes to HIGH. In order to avoid wrong

state detection, an external capacitor is not allowed and if using an external pull-up or pull-down resistor, it is recommended to use less than 10

kΩ

respectively. For floating state resistance between SS and GND, it

needs to be higher than 2MΩ. When Float state is desired, it is recommended

to use as minimum trace as possible (< 0.01in) to avoid noise coupling by adjacent signal and minimize parasitic capacitance. Please refer to PCB

Layout Example.

The input inrush current can be controlled by selecting appropriate soft-start time. The table below shows the slew rate on VOUT by VSS conditions

as follows.

VSS

Slew Rate

Unit

HIGH (> 1.05V)

2

mV/us

LOW (< 0.5V)

1

Floating (> 2

MΩ)

16.7

QUICK OUTPUT DISAHRGE (QOD)

The AP22980 includes a QOD (Quick Output Discharge) feature with typical 50

Ω of an internal discharge resistor. When the switch is disabled by

EN pin or switch is enabled and during ON delay time (tDON), an internal discharge resistor is connected between VOUT and GND to remove the

remaining charge from the output. Even if the switch is in OFF state without valid VBIAS, QOD stays working.

VBIAS

EN

QOD

Device

Invalid

Don’t Care

ON

OFF

Valid

LOW

ON

Disabled

LOW to HIGH

ON for tDON

Enabled and in soft-start

HIGH

OFF

Enabled

THERMAL CONSIDERATOIN

The maximum junction temperature should be restricted to +150°C under normal operating conditions. The maximum allowable power dissipation

PD(MAX) can be calculated as:

PD(MAX) = (TJ(MAX) - TA) / θJA

where,

TJ(MAX) is the maximum operating junction temperature. For AP22980, TJ(MAX) = +150°C.

TA is the ambient temperature of the device.

θJA is the junction-to-air thermal impedance.

BOARD LAYOUT

Good PCB layout is important for improving the thermal performance of the device. All trace lengths should be kept as short as possible. Place

input and output capacitors close to the device to minimize the effects of parasitic inductance. The input and output PCB traces should be as wide

as possible. SS pin must have minimum trace length (< 0.1in) for float pin configuration to avoid unexpected coupling from adjacent signal.