AP61200/AP61201/AP61202/AP61203

Document number: DS44251 Rev. 3 - 2

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AP61200/AP61201/AP61202/AP61203

Application Information (continued)

4

Power-Good (PG) Indicator (AP61202/AP61203)

The PG pin of AP61202/AP61203 is an open-drain output that is actively held low during the soft-start period until the output voltage reaches 95%

of its target value. When the output voltage is outside of its regulation by ±10%, PG pulls low until the output returns within 5% of its set value. The

PG rising edge transition is delayed by

55μs. The PG pin is connected to VIN through an internal 5MΩ pull-up resistor.

5

Undervoltage Lockout (UVLO) and Input Overvoltage Protection (OVP)

Undervoltage lockout is implemented to protect the IC from insufficient input voltages. The AP61200/AP61201/AP61202/AP61203 disables if the

input voltage falls below 1.84V. In this UVLO event, both the high-side and low-side power MOSFETs turn

off and the 1kΩ active discharge

enables to discharge the output voltage to ground.

Similarly, input overvoltage protection is implemented to protect the IC from excess input voltages. The AP61200/AP61201/AP61202/AP61203

disables if the input voltage rises above 6.3V. In this OVP event, both the high-side and low-side power MOSFETs turn off

and the 1kΩ active

discharge enables to discharge the output voltage to ground.

6

Overcurrent Protection (OCP)

The AP61200/AP61201/AP61202/AP61203 has cycle-by-cycle valley current limit protection by sensing the current through the internal low-side

power MOSFET, Q2. While Q2 is on, the internal sensing circuitry monitors its conduction current. The overcurrent limit has a corresponding

voltage limit, VLIMIT. When the voltage between GND and SW is lower than VLIMIT due to excessive current through Q2, the OCP triggers, and the

controller turns off Q2. During this time, both Q1 and Q2 remain off. A new switching cycle begins only when the voltage between GND and SW

rises above VLIMIT. If Q2 consistently hits the valley current limit for 0.6ms, the buck converter enters hiccup mode and shuts down. After 3.4ms of

down time, the buck converter restarts powering up. Hiccup mode reduces the power dissipation in the overcurrent condition.

The AP61200/AP61201/AP61202/AP61203 also has cycle-by-cycle peak current limit protection by sensing the current through the internal high-

side power MOSFET, Q1, through a similar mechanism as the cycle-by-cycle valley current limit protection.

Because the RDS(ON) values of the power MOSFETs increase with temperature, VLIMIT has a temperature coefficient of 0.4%/°C to compensate for

the temperature dependency of RDS(ON).

7

Thermal Shutdown (TSD)

If the junction temperature of the device reaches the thermal shutdown limit of +160°C, the AP61200/AP61201/AP61202/AP61203 shuts down

both its high-side and low-side power MOSFETs and triggers the output active discharge. When the junction temperature reduces to the required

level (+130°C typical), the device initiates a normal power-up cycle with soft-start.