AP3981C

Document number: DS41619 Rev. 2 - 2

12 of 16

www.diodes.com

June 2019

© Diodes Incorporated

AP3981C

Operation Description (continued)

9.

VCS Jitter

Even though the valley turn on function produces the random frequency jitter feature, an active frequency jitter function is added in the

AP3981C. The active frequency dithering is realized by applying variation on VCS reference (VCS_REF). The VCS_REF is changed every 2 cycles

and the period of variation is 12 cycles, which is shown as Figure 4. The variation between VCS4 and VCS1 is +/-2% using the mean level as a

reference.

Figure 4. VCS Jitter

10. Adjustable Line Compensation

In real system, there exists a delay time, from the VSOURCE reach the inner VCS threshold to the actual switch turn-off point. The delay time

contains the propagation time of the inner comparator and the driver delay, and it does not change with line voltage. The delay time leads to

different primary peak current under different line voltage, which results in different output current in CC mode.

RFB1

RFB2

FB

PFM

VAUX

VPP

VCS_REF

R1

R2

RS

RLC

VLC

Inside

AP3981C

Figure 5. Line Compensation Control Circuit

In order to alleviate the difference under the universal input voltage, the AP3981C integrates the line compensation control circuit shown as

Figure 5. During the primary on stage, an inner switcher RS switches on, the RLC is much smaller compared with RFB2, so the RFB2’s effect on

line compensation can be neglected, the proportional line voltage is detected through RFB1 and RLC and is added to the VCS threshold (VCS_REF).

The VLC can be derived from the Formula 7:

(7)

VCS1

VCS2

VCS3

VCS4

VCS3

VCS2

VCS1

VCS2

VCS3

VCS4

VCS3

VCS2

VCS1

Mean Level

LC

1

FB

1

FB

AUX

PP

1

FB

LC

R

R

2

R

*

3

R

1

V

V

*

2

R

*

3

R

V







