LMK04832MPAPSEP datasheet(34/102 Pages) TI

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8.3.8.3 Exiting Holdover

Holdover mode can be exited in one of two ways.

• Manually, by programming the device from the host.

• Automatically, when the LOS signal unasserts for a clock that provides a valid input to PLL1.

8.3.8.4 Holdover Frequency Accuracy and DAC Performance

When in holdover mode, PLL1 runs in open loop and the DAC sets the CPout1 voltage. If fixed CPout1 mode

is used, then the output of the DAC is dependent upon the MAN_DAC register. If tracked CPout1 mode is used,

then the output of the DAC is approximately the same voltage at the CPout1 pin before holdover mode was

entered. When using Tracked mode and MAN_DAC_EN = 1, the DAC value during holdover is loaded with the

programmed value in MAN_DAC and not the tracked value.

When in Tracked CPout1 mode, the DAC has a worst-case tracking error of ±2 LSBs once PLL1 tuning voltage

is acquired. The step size is approximately 3.2 mV, therefore the VCXO frequency error during holdover mode

caused by the DAC tracking accuracy is ±6.4 mV × Kv, where Kv is the tuning sensitivity of the VCXO in use.

Therefore, the accuracy of the system when in holdover mode in ppm is:

Holdover accuracy (ppm) =

± 6.4 mV × Kv × 1e6

VCXO Frequency

(2)

As an example, consider a system with a 19.2-MHz clock input, a 153.6-MHz VCXO with a Kv of 17 kHz/V. The

accuracy of the system in holdover in ppm is:

±0.71 ppm = ±6.4 mV × 17 kHz/V × 1e6 / 153.6 MHz

(3)

It is important to account for this frequency error when determining the allowable frequency error window to

cause holdover mode to exit.

8.3.9 PLL2 Loop Filter

PLL2 has an integrated loop filter of C1i = 60 pF, R3 = 2400 Ω, C3 = 50 pF, R4 = 200 Ω and C4 = 10 pF

as shown in Figure 8-9. Loop filter components C1, C2, and R2 can be solved using TI software. See Device

Support for more information.

Figure 8-9. PLL2 On-Chip Loop Filter

LMK04832-SEP

SNAS838A – OCTOBER 2022 – REVISED NOVEMBER 2022

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LMK04832MPAPSEP Datasheet(PDF) 34 Page - Texas Instruments