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LMK04832MPAPSEP Datasheet(PDF) 60 Page - Texas Instruments |
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LMK04832MPAPSEP Datasheet(HTML) 60 Page - Texas Instruments |
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60 / 102 page  8.6.2.3.11 SYNC_DISSYSREF, SYNC_DISX SYNC_DISX will prevent a clock output from being synchronized or interrupted by a SYNC event or when outputting SYSREF. Table 8-40. Register 0x144 BIT NAME POR DEFAULT DESCRIPTION 7 SYNC_DISSYSREF 0 Prevent the SYSREF clocks from becoming synchronized during a SYNC event. If SYNC_DISSYSREF is enabled, the device will continue to operate normally during a SYNC event. 6 SYNC_DIS12 0 Prevent the device clock output from becoming synchronized during a SYNC event or SYSREF clock. If SYNC_DIS bit for a particular output is enabled, then the device will continue to operate normally during a SYNC event or SYSREF clock. 5 SYNC_DIS10 0 4 SYNC_DIS8 0 3 SYNC_DIS6 0 2 SYNC_DIS4 0 1 SYNC_DIS2 0 0 SYNC_DIS0 0 8.6.2.3.12 PLL1R_SYNC_EN, PLL1R_SYNC_SRC, PLL2R_SYNC_EN, FIN0_DIV2_EN, FIN0_INPUT_TYPE These bits are used when synchronizing PLL1 and PLL2 R dividers. Table 8-41. Register 0x145 BIT NAME POR DEFAULT DESCRIPTION 7 NA 0 Reserved 6 PLL1R_SYNC_EN 0 Enable synchronization for PLL1 R divider 0: Not enabled 1: Enabled 5:4 PLL1R_SYNC_SRC 0 Select the source for PLL1 R divider synchronization Field Value Definition 0 (0x00) Reserved 1 (0x01) SYNC Pin 2 (0x02) CLKIN0 3 (0x03) Reserved 3 PLL2R_SYNC_EN 0 Enable synchronization for PLL2 R divider. Synchronization for PLL2 R always comes from the SYNC pin. 0: Not enabled 1: Enabled 2 FIN0_DIV2_EN 0 Sets the input path to use or bypass the divide-by-2. 0: Bypassed (÷1) 1: Divided (÷2) 1:0 FIN0_INPUT_TYPE 0 Program input type to hardware interface used. Field Value Definition 0 (0x00) Differential Input 1 (0x01) Single Ended Input (FIN0_P) 2 (0x02) Single Ended Input (FIN0_N) 3 (0x03) Reserved LMK04832-SEP SNAS838A – OCTOBER 2022 – REVISED NOVEMBER 2022 www.ti.com 60 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: LMK04832-SEP |
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